[llvm-commits] [llvm] r42874 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td

[Dale Johannesen]

Author: johannes
Date: Thu Oct 11 15:58:37 2007
New Revision: 42874

URL: http://llvm.org/viewvc/llvm-project?rev=42874&view=rev
Log:
Add missing argument to PALIGNR


Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=42874&r1=42873&r2=42874&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Oct 11 15:58:37 2007
@@ -2598,14 +2598,14 @@
 let isTwoAddress = 1 in {
   def PALIGNR64rr  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
                            (ins VR64:$src1, VR64:$src2, i16imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR64:$dst,
                              (int_x86_ssse3_palign_r
                               VR64:$src1, VR64:$src2,
                               imm:$src3))]>;
   def PALIGNR64rm  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
                            (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR64:$dst,
                              (int_x86_ssse3_palign_r
                               VR64:$src1,
@@ -2614,14 +2614,14 @@
 
   def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
                            (ins VR128:$src1, VR128:$src2, i32imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR128:$dst,
                              (int_x86_ssse3_palign_r_128
                               VR128:$src1, VR128:$src2,
                               imm:$src3))]>, OpSize;
   def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
                            (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR128:$dst,
                              (int_x86_ssse3_palign_r_128
                               VR128:$src1,