[llvm-commits] [llvm] r42453 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/SelectionDAG/ScheduleDAG.cpp lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Evan Cheng
evan.cheng at apple.com
Fri Sep 28 15:32:30 PDT 2007
Author: evancheng
Date: Fri Sep 28 17:32:30 2007
New Revision: 42453
URL: http://llvm.org/viewvc/llvm-project?rev=42453&view=rev
Log:
If two instructions are both two-address code, favors (schedule closer to
terminator) the one that has a CopyToReg use. This fixes
2006-05-11-InstrSched.ll with -new-cc-modeling-scheme.
Modified:
llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=42453&r1=42452&r2=42453&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Fri Sep 28 17:32:30 2007
@@ -115,7 +115,7 @@
short NumSuccsLeft; // # of succs not scheduled.
bool isTwoAddress : 1; // Is a two-address instruction.
bool isCommutable : 1; // Is a commutable instruction.
- bool hasImplicitDefs : 1; // Has implicit physical reg defs.
+ bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
bool isPending : 1; // True once pending.
bool isAvailable : 1; // True once available.
bool isScheduled : 1; // True once scheduled.
@@ -129,7 +129,7 @@
SUnit(SDNode *node, unsigned nodenum)
: Node(node), InstanceNo(0), NodeNum(nodenum), Latency(0),
NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
- isTwoAddress(false), isCommutable(false), hasImplicitDefs(false),
+ isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
isPending(false), isAvailable(false), isScheduled(false),
CycleBound(0), Cycle(0), Depth(0), Height(0),
CopyDstRC(NULL), CopySrcRC(NULL) {}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp?rev=42453&r1=42452&r2=42453&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Sep 28 17:32:30 2007
@@ -63,7 +63,7 @@
SU->Latency = Old->Latency;
SU->isTwoAddress = Old->isTwoAddress;
SU->isCommutable = Old->isCommutable;
- SU->hasImplicitDefs = Old->hasImplicitDefs;
+ SU->hasPhysRegDefs = Old->hasPhysRegDefs;
SUnitMap[Old->Node].push_back(SU);
return SU;
}
@@ -167,8 +167,6 @@
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
const TargetInstrDescriptor &TID = TII->get(Opc);
- if (TID.ImplicitDefs)
- SU->hasImplicitDefs = true;
for (unsigned i = 0; i != TID.numOperands; ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
@@ -185,8 +183,10 @@
for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
SDNode *N = SU->FlaggedNodes[n];
- if (N->isTargetOpcode() && TII->getImplicitDefs(N->getTargetOpcode()))
- SU->hasImplicitDefs = true;
+ if (N->isTargetOpcode() &&
+ TII->getImplicitDefs(N->getTargetOpcode()) &&
+ CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode()))
+ SU->hasPhysRegDefs = true;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
SDNode *OpN = N->getOperand(i).Val;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=42453&r1=42452&r2=42453&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Sep 28 17:32:30 2007
@@ -1144,10 +1144,26 @@
}
+/// hasCopyToRegUse - Return true if SU has a value successor that is a
+/// CopyToReg node.
+static bool hasCopyToRegUse(SUnit *SU) {
+ for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
+ I != E; ++I) {
+ if (I->isCtrl) continue;
+ SUnit *SuccSU = I->Dep;
+ if (SuccSU->Node && SuccSU->Node->getOpcode() == ISD::CopyToReg)
+ return true;
+ }
+ return false;
+}
+
/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
/// it as a def&use operand. Add a pseudo control edge from it to the other
/// node (if it won't create a cycle) so the two-address one will be scheduled
-/// first (lower in the schedule).
+/// first (lower in the schedule). If both nodes are two-address, favor the
+/// one that has a CopyToReg use (more likely to be a loop induction update).
+/// If both are two-address, but one is commutable while the other is not
+/// commutable, favor the one that's not commutable.
template<class SF>
void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
@@ -1156,7 +1172,7 @@
continue;
SDNode *Node = SU->Node;
- if (!Node || !Node->isTargetOpcode())
+ if (!Node || !Node->isTargetOpcode() || SU->FlaggedNodes.size() > 0)
continue;
unsigned Opc = Node->getTargetOpcode();
@@ -1173,12 +1189,13 @@
SUnit *SuccSU = I->Dep;
// Don't constraint nodes with implicit defs. It can create cycles
// plus it may increase register pressures.
- if (SuccSU == SU || SuccSU->hasImplicitDefs)
+ if (SuccSU == SU || SuccSU->hasPhysRegDefs)
continue;
// Be conservative. Ignore if nodes aren't at the same depth.
if (SuccSU->Depth != SU->Depth)
continue;
if ((!canClobber(SuccSU, DUSU) ||
+ (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) ||
(!SU->isCommutable && SuccSU->isCommutable)) &&
!isReachable(SuccSU, SU)) {
DOUT << "Adding an edge from SU # " << SU->NodeNum
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