[llvm-commits] [llvm] r42271 - in /llvm/trunk/lib/Target/Mips: MipsAsmPrinter.cpp MipsISelDAGToDAG.cpp MipsInstrInfo.td

[Bruno Cardoso Lopes]

Author: bruno
Date: Mon Sep 24 15:15:11 2007
New Revision: 42271

URL: http://llvm.org/viewvc/llvm-project?rev=42271&view=rev
Log:
Added "LoadEffective" pattern to handle stack locations.
Fixed some comments

Modified:
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=42271&r1=42270&r2=42271&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Mon Sep 24 15:15:11 2007
@@ -141,7 +141,7 @@
   #endif
 
   unsigned int Bitmask = getSavedRegsBitmask(false, MF);
-  O << "\t.mask\t"; 
+  O << "\t.mask \t"; 
   printHex32(Bitmask);
   O << "," << Offset << "\n";
 }
@@ -366,9 +366,16 @@
 void MipsAsmPrinter::
 printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier) 
 {
-  // lw/sw $reg, MemOperand
-  // will turn into :
-  // lw/sw $reg, imm($reg)
+  // when using stack locations for not load/store instructions
+  // print the same way as all normal 3 operand instructions.
+  if (Modifier && !strcmp(Modifier, "stackloc")) {
+    printOperand(MI, opNum+1);
+    O << ", ";
+    printOperand(MI, opNum);
+    return;
+  }
+
+  // Load/Store memory operands -- imm($reg)
   printOperand(MI, opNum);
   O << "(";
   printOperand(MI, opNum+1);

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=42271&r1=42270&r2=42271&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Sep 24 15:15:11 2007
@@ -196,8 +196,8 @@
   }
 
   ///
-  // Instruction Selection not handled by custom or by the 
-  // auto-generated tablegen selection should be handled here
+  // Instruction Selection not handled by the auto-generated 
+  // tablegen selection should be handled here.
   /// 
   switch(Opcode) {
 

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=42271&r1=42270&r2=42271&view=diff

==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Sep 24 15:15:11 2007
@@ -332,6 +332,12 @@
       !strconcat(instr_asm, " $dst, $src"), 
       [], IIAlu>;
 
+class EffectiveAddress<string instr_asm> : 
+  FI<0x09, 
+     (outs CPURegs:$dst), 
+     (ins mem:$addr),
+     instr_asm,
+     [(set CPURegs:$dst, addr:$addr)], IIAlu>;
 
 //===----------------------------------------------------------------------===//
 // Pseudo instructions
@@ -468,6 +474,12 @@
                 "jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
 }
 
+// FrameIndexes are legalized when they are operands from load/store 
+// instructions. The same not happens for stack address copies, so an
+// add op with mem ComplexPattern is used and the stack address copy
+// can be matched. It's similar to Sparc LEA_ADDRi
+def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//