[llvm-commits] [llvm] r41191 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

[Dan Gohman]

Author: djg
Date: Mon Aug 20 14:28:38 2007
New Revision: 41191

URL: http://llvm.org/viewvc/llvm-project?rev=41191&view=rev
Log:
Minor cleanups to reduce some spurious differences between different
scheduler implementations.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=41191&r1=41190&r2=41191&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Aug 20 14:28:38 2007
@@ -45,7 +45,6 @@
 /// ScheduleDAGRRList - The actual register reduction list scheduler
 /// implementation.  This supports both top-down and bottom-up scheduling.
 ///
-
 class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
 private:
   /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
@@ -95,7 +94,7 @@
   CalculateHeights();
 
   AvailableQueue->initNodes(SUnitMap, SUnits);
-
+  
   // Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
   if (isBottomUp)
     ListScheduleBottomUp();
@@ -103,7 +102,7 @@
     ListScheduleTopDown();
   
   AvailableQueue->releaseState();
-
+  
   CommuteNodesToReducePressure();
   
   DOUT << "*** Final schedule ***\n";
@@ -169,7 +168,7 @@
 //===----------------------------------------------------------------------===//
 
 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
-/// the Available queue is the count reaches zero. Also update its cycle bound.
+/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
 void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain, 
                                     unsigned CurCycle) {
   // FIXME: the distance between two nodes is not always == the predecessor's
@@ -233,7 +232,7 @@
   AvailableQueue->push(SUnitMap[DAG.getRoot().Val]);
 
   // While Available queue is not empty, grab the node with the highest
-  // priority. If it is not ready put it back. Schedule the node.
+  // priority. If it is not ready put it back.  Schedule the node.
   std::vector<SUnit*> NotReady;
   while (!AvailableQueue->empty()) {
     SUnit *CurNode = AvailableQueue->pop();
@@ -282,7 +281,7 @@
 //===----------------------------------------------------------------------===//
 
 /// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
-/// the PendingQueue if the count reaches zero.
+/// the AvailableQueue if the count reaches zero. Also update its cycle bound.
 void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain, 
                                     unsigned CurCycle) {
   // FIXME: the distance between two nodes is not always == the predecessor's
@@ -330,6 +329,8 @@
   SU->isScheduled = true;
 }
 
+/// ListScheduleTopDown - The main loop of list scheduling for top-down
+/// schedulers.
 void ScheduleDAGRRList::ListScheduleTopDown() {
   unsigned CurCycle = 0;
   SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
@@ -348,7 +349,7 @@
   CurCycle++;
 
   // While Available queue is not empty, grab the node with the highest
-  // priority. If it is not ready put it back. Schedule the node.
+  // priority. If it is not ready put it back.  Schedule the node.
   std::vector<SUnit*> NotReady;
   while (!AvailableQueue->empty()) {
     SUnit *CurNode = AvailableQueue->pop();
@@ -474,7 +475,7 @@
 
     const TargetInstrInfo *TII;
   public:
-    BURegReductionPriorityQueue(const TargetInstrInfo *tii)
+    explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii)
       : TII(tii) {}
 
     void initNodes(DenseMap<SDNode*, SUnit*> &sumap,
@@ -539,7 +540,8 @@
 
 
   template<class SF>
-  class TDRegReductionPriorityQueue : public RegReductionPriorityQueue<SF> {
+  class VISIBILITY_HIDDEN TDRegReductionPriorityQueue
+   : public RegReductionPriorityQueue<SF> {
     // SUnitMap SDNode to SUnit mapping (n -> 1).
     DenseMap<SDNode*, SUnit*> *SUnitMap;