[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

[Dan Gohman]

Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.133 -> 1.134
---
Log message:

Add new TargetLowering code to provide the final register type that an
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.

Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.


---
Diffs of the changes:  (+20 -5)

 TargetLowering.h |   25 ++++++++++++++++++++-----
 1 files changed, 20 insertions(+), 5 deletions(-)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.133 llvm/include/llvm/Target/TargetLowering.h:1.134
--- llvm/include/llvm/Target/TargetLowering.h:1.133	Wed Jun 27 11:08:04 2007
+++ llvm/include/llvm/Target/TargetLowering.h	Thu Jun 28 18:29:44 2007
@@ -212,12 +212,13 @@
   /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
   ///
   /// This method returns the number of registers needed, and the VT for each
-  /// register.  It also returns the VT of the VectorType elements before they
-  /// are promoted/expanded.
+  /// register.  It also returns the VT and quantity of the intermediate values
+  /// before they are promoted/expanded.
   ///
   unsigned getVectorTypeBreakdown(MVT::ValueType VT, 
-                                  MVT::ValueType &ElementVT,
-                                  MVT::ValueType &LegalElementVT) const;
+                                  MVT::ValueType &IntermediateVT,
+                                  unsigned &NumIntermediates,
+                                  MVT::ValueType &RegisterVT) const;
   
   typedef std::vector<double>::const_iterator legal_fpimm_iterator;
   legal_fpimm_iterator legal_fpimm_begin() const {
@@ -360,6 +361,18 @@
     return VT == MVT::iPTR ? PointerTy : VT;
   }
 
+  /// getRegisterType - Return the type of registers that this ValueType will
+  /// eventually require.
+  MVT::ValueType getRegisterType(MVT::ValueType VT) const {
+    if (!MVT::isExtendedVT(VT))
+      return RegisterTypeForVT[VT];
+           
+    MVT::ValueType VT1, RegisterVT;
+    unsigned NumIntermediates;
+    (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
+    return RegisterVT;
+  }
+  
   /// getNumRegisters - Return the number of registers that this ValueType will
   /// eventually require.  This is one for any types promoted to live in larger
   /// registers, but may be more than one for types (like i64) that are split
@@ -369,7 +382,8 @@
       return NumRegistersForVT[VT];
            
     MVT::ValueType VT1, VT2;
-    return getVectorTypeBreakdown(VT, VT1, VT2);
+    unsigned NumIntermediates;
+    return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
   }
   
   /// hasTargetDAGCombine - If true, the target has custom DAG combine
@@ -1034,6 +1048,7 @@
   /// each ValueType the target supports natively.
   TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
   unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
+  MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
 
   /// TransformToType - For any value types we are promoting or expanding, this
   /// contains the value type that we are changing to.  For Expanded types, this