[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrInfo.td ARMInstrThumb.td

[Dan Gohman]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.cpp updated: 1.39 -> 1.40
ARMInstrInfo.h updated: 1.16 -> 1.17
ARMInstrInfo.td updated: 1.114 -> 1.115
ARMInstrThumb.td updated: 1.32 -> 1.33
---
Log message:

Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).


---
Diffs of the changes:  (+5 -15)

 ARMInstrInfo.cpp |   14 --------------
 ARMInstrInfo.h   |    1 -
 ARMInstrInfo.td  |    4 ++++
 ARMInstrThumb.td |    1 +
 4 files changed, 5 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.39 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.40
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.39	Mon Jun 18 20:48:04 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp	Mon Jun 25 19:48:06 2007
@@ -130,20 +130,6 @@
   return 0;
 }
 
-bool ARMInstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const {
-  switch (MI->getOpcode()) {
-  default: break;
-  case ARM::LDRcp:
-  case ARM::MOVi:
-  case ARM::MVNi:
-  case ARM::MOVi2pieces:
-  case ARM::tLDRcp:
-    // These instructions are always trivially rematerializable.
-    return true;
-  }
-  return false;
-}
-
 static unsigned getUnindexedOpcode(unsigned Opc) {
   switch (Opc) {
   default: break;


Index: llvm/lib/Target/ARM/ARMInstrInfo.h
diff -u llvm/lib/Target/ARM/ARMInstrInfo.h:1.16 llvm/lib/Target/ARM/ARMInstrInfo.h:1.17
--- llvm/lib/Target/ARM/ARMInstrInfo.h:1.16	Mon Jun 18 20:48:04 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.h	Mon Jun 25 19:48:06 2007
@@ -87,7 +87,6 @@
                            unsigned &SrcReg, unsigned &DstReg) const;
   virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
   virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
-  virtual bool isTriviallyReMaterializable(MachineInstr *MI) const;
   
   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
                                               MachineBasicBlock::iterator &MBBI,


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.114 llvm/lib/Target/ARM/ARMInstrInfo.td:1.115
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.114	Fri Jun 22 11:59:54 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Mon Jun 25 19:48:06 2007
@@ -677,6 +677,7 @@
                [(set GPR:$dst, (load addrmode2:$addr))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
+let isReMaterializable = 1 in
 def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
                  "ldr", " $dst, $addr", []>;
 
@@ -810,6 +811,7 @@
 def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
                 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
 
+let isReMaterializable = 1 in
 def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
                 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
 
@@ -917,6 +919,7 @@
                 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
 def  MVNs  : AI<(ops GPR:$dst, so_reg:$src),
                 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
+let isReMaterializable = 1 in
 def  MVNi  : AI<(ops GPR:$dst, so_imm:$imm),
                 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
 
@@ -1187,6 +1190,7 @@
 // Large immediate handling.
 
 // Two piece so_imms.
+let isReMaterializable = 1 in
 def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
                          "mov", " $dst, $src",
                          [(set GPR:$dst, so_imm2part:$src)]>;


Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.32 llvm/lib/Target/ARM/ARMInstrThumb.td:1.33
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.32	Mon Jun 18 20:48:04 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.td	Mon Jun 25 19:48:06 2007
@@ -267,6 +267,7 @@
                   [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
+let isReMaterializable = 1 in
 def tLDRcp  : TIs<(ops GPR:$dst, i32imm:$addr),
                   "ldr $dst, $addr", []>;
 } // isLoad