[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h

[Dan Gohman]

Changes in directory llvm/include/llvm/Target:

TargetLowering.h updated: 1.127 -> 1.128
---
Log message:

Rename TargetLowering::getNumElements and friends to
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.


---
Diffs of the changes:  (+4 -4)

 TargetLowering.h |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.127 llvm/include/llvm/Target/TargetLowering.h:1.128
--- llvm/include/llvm/Target/TargetLowering.h:1.127	Fri Jun  1 03:25:24 2007
+++ llvm/include/llvm/Target/TargetLowering.h	Thu Jun 21 09:42:22 2007
@@ -347,12 +347,12 @@
     return VT == MVT::iPTR ? PointerTy : VT;
   }
 
-  /// getNumElements - Return the number of registers that this ValueType will
+  /// getNumRegisters - Return the number of registers that this ValueType will
   /// eventually require.  This is one for any types promoted to live in larger
   /// registers, but may be more than one for types (like i64) that are split
   /// into pieces.
-  unsigned getNumElements(MVT::ValueType VT) const {
-    return NumElementsForVT[VT];
+  unsigned getNumRegisters(MVT::ValueType VT) const {
+    return NumRegistersForVT[VT];
   }
   
   /// hasTargetDAGCombine - If true, the target has custom DAG combine
@@ -1035,7 +1035,7 @@
   /// RegClassForVT - This indicates the default register class to use for
   /// each ValueType the target supports natively.
   TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
-  unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
+  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
 
   /// TransformToType - For any value types we are promoting or expanding, this
   /// contains the value type that we are changing to.  For Expanded types, this