[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.cpp X86InstrInfo.h X86InstrInfo.td X86InstrMMX.td X86InstrSSE.td
Dan Gohman
djg at cray.com
Mon Jun 18 18:48:39 PDT 2007
Changes in directory llvm/lib/Target/X86:
X86InstrFPStack.td updated: 1.9 -> 1.10
X86InstrInfo.cpp updated: 1.91 -> 1.92
X86InstrInfo.h updated: 1.66 -> 1.67
X86InstrInfo.td updated: 1.307 -> 1.308
X86InstrMMX.td updated: 1.32 -> 1.33
X86InstrSSE.td updated: 1.183 -> 1.184
---
Log message:
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
---
Diffs of the changes: (+23 -19)
X86InstrFPStack.td | 2 --
X86InstrInfo.cpp | 14 +++++++++++++-
X86InstrInfo.h | 2 +-
X86InstrInfo.td | 2 --
X86InstrMMX.td | 14 ++++++--------
X86InstrSSE.td | 8 +++-----
6 files changed, 23 insertions(+), 19 deletions(-)
Index: llvm/lib/Target/X86/X86InstrFPStack.td
diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.9 llvm/lib/Target/X86/X86InstrFPStack.td:1.10
--- llvm/lib/Target/X86/X86InstrFPStack.td:1.9 Tue Mar 20 19:16:56 2007
+++ llvm/lib/Target/X86/X86InstrFPStack.td Mon Jun 18 20:48:04 2007
@@ -413,12 +413,10 @@
def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
// Floating point constant loads.
-let isReMaterializable = 1 in {
def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
[(set RFP:$dst, fp64imm0)]>;
def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
[(set RFP:$dst, fp64imm1)]>;
-}
def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.91 llvm/lib/Target/X86/X86InstrInfo.cpp:1.92
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.91 Thu Jun 14 17:03:45 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cpp Mon Jun 18 20:48:04 2007
@@ -112,9 +112,20 @@
}
-bool X86InstrInfo::isOtherReMaterializableLoad(MachineInstr *MI) const {
+bool X86InstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const {
switch (MI->getOpcode()) {
default: break;
+ case X86::FpLD0:
+ case X86::FpLD1:
+ case X86::MOV8ri:
+ case X86::MOV16ri:
+ case X86::MOV32ri:
+ case X86::MMX_V_SET0:
+ case X86::MMX_V_SETALLONES:
+ case X86::V_SET0:
+ case X86::V_SETALLONES:
+ // These instructions are always trivially rematerializable.
+ return true;
case X86::MOV8rm:
case X86::MOV16rm:
case X86::MOV16_rm:
@@ -128,6 +139,7 @@
case X86::MOVAPDrm:
case X86::MMX_MOVD64rm:
case X86::MMX_MOVQ64rm:
+ // Loads from constant pools are trivially rematerializable.
return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
MI->getOperand(1).getReg() == 0 &&
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.66 llvm/lib/Target/X86/X86InstrInfo.h:1.67
--- llvm/lib/Target/X86/X86InstrInfo.h:1.66 Thu Jun 14 17:03:45 2007
+++ llvm/lib/Target/X86/X86InstrInfo.h Mon Jun 18 20:48:04 2007
@@ -239,7 +239,7 @@
unsigned& destReg) const;
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
- bool isOtherReMaterializableLoad(MachineInstr *MI) const;
+ bool isTriviallyReMaterializable(MachineInstr *MI) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.307 llvm/lib/Target/X86/X86InstrInfo.td:1.308
--- llvm/lib/Target/X86/X86InstrInfo.td:1.307 Sat May 5 23:00:55 2007
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Jun 18 20:48:04 2007
@@ -617,7 +617,6 @@
"mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
"mov{l} {$src, $dst|$dst, $src}", []>;
-let isReMaterializable = 1 in {
def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
"mov{b} {$src, $dst|$dst, $src}",
[(set GR8:$dst, imm:$src)]>;
@@ -627,7 +626,6 @@
def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
"mov{l} {$src, $dst|$dst, $src}",
[(set GR32:$dst, imm:$src)]>;
-}
def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
"mov{b} {$src, $dst|$dst, $src}",
[(store (i8 imm:$src), addr:$dst)]>;
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.32 llvm/lib/Target/X86/X86InstrMMX.td:1.33
--- llvm/lib/Target/X86/X86InstrMMX.td:1.32 Wed May 16 01:08:17 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Mon Jun 18 20:48:05 2007
@@ -503,14 +503,12 @@
// Alias instructions that map zero vector to pxor.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-let isReMaterializable = 1 in {
- def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
- "pxor $dst, $dst",
- [(set VR64:$dst, (v1i64 immAllZerosV))]>;
- def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
- "pcmpeqd $dst, $dst",
- [(set VR64:$dst, (v1i64 immAllOnesV))]>;
-}
+def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
+ "pxor $dst, $dst",
+ [(set VR64:$dst, (v1i64 immAllZerosV))]>;
+def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
+ "pcmpeqd $dst, $dst",
+ [(set VR64:$dst, (v1i64 immAllOnesV))]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.183 llvm/lib/Target/X86/X86InstrSSE.td:1.184
--- llvm/lib/Target/X86/X86InstrSSE.td:1.183 Thu May 17 13:44:37 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td Mon Jun 18 20:48:05 2007
@@ -759,7 +759,6 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-let isReMaterializable = 1 in
def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
"xorps $dst, $dst",
[(set VR128:$dst, (v4f32 immAllZerosV))]>;
@@ -1819,10 +1818,9 @@
// Alias instructions that map zero vector to pxor / xorp* for sse.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-let isReMaterializable = 1 in
- def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
- "pcmpeqd $dst, $dst",
- [(set VR128:$dst, (v2f64 immAllOnesV))]>;
+def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
+ "pcmpeqd $dst, $dst",
+ [(set VR128:$dst, (v2f64 immAllOnesV))]>;
// FR64 to 128-bit vector conversion.
def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
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