[llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp VirtRegMap.cpp

[Evan Cheng]

We can eliminate LDRcp, that's fine.

However, I still don't like the separate hook and targetinstrinfo  
bit. Dan, can you have just a single isTriviallyReMaterializable hook  
that encompass all these?

Evan

On Jun 18, 2007, at 9:42 AM, Chris Lattner wrote:

>
> On Jun 18, 2007, at 7:46 AM, Dan Gohman wrote:
>
>>> Is this necessary? ARM is already doing this by marking trivially  
>>> re-
>>> materializable instructions with let isReMaterializable = 1.
>>
>> It's not necessary, but it seems cleaner :-).
>>
>> In the ARM target, other than instructions that are always trivially
>> rematerialiable, there's only LDR, with a ReMaterializable clone
>> named LDRcp.
>> x86 has a variety of load instructions, so in order to work the way
>> ARM does
>> x86 would need a varity of clones, and then the clones wouldn't be
>> able to
>> use the automatic instruction selection, so there would still need
>> to be some
>> new custom logic for picking which clone to use for each constant.
>
> Ah, good point.  Evan, do you think the LDRcp instruction can be
> eliminated now?
>
> -Chris
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