[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Dan Gohman]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.459 -> 1.460
---
Log message:

When creating CopyFromReg nodes, always use legal types. And use the
correct types for the result vector, even though it is currently bitcasted
to a different type immediately.


---
Diffs of the changes:  (+6 -6)

 SelectionDAGISel.cpp |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.459 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.460
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.459	Wed Jun 13 00:51:31 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Jun 13 09:55:16 2007
@@ -772,7 +772,7 @@
       // If the register was promoted, use TRUNCATE or FP_ROUND as appropriate.
       for (unsigned i = 0; i != NE; ++i) {
         SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 
-                                          PTyElementVT);
+                                          PTyLegalElementVT);
         if (MVT::isFloatingPoint(PTyElementVT))
           Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
         else
@@ -782,17 +782,17 @@
     } else {
       // If the register was expanded, use BUILD_PAIR.
       assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
-      for (unsigned i = 0; i != NE/2; ++i) {
+      for (unsigned i = 0; i != NE; ++i) {
         SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 
-                                           PTyElementVT);
+                                           PTyLegalElementVT);
         SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, 
-                                           PTyElementVT);
-        Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
+                                           PTyLegalElementVT);
+        Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, PTyElementVT, Op0, Op1));
       }
     }
     
     Ops.push_back(DAG.getConstant(NE, MVT::i32));
-    Ops.push_back(DAG.getValueType(PTyLegalElementVT));
+    Ops.push_back(DAG.getValueType(PTyElementVT));
     N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
     
     // Finally, use a VBIT_CONVERT to make this available as the appropriate