[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp ARMInstrInfo.h ARMLoadStoreOptimizer.cpp ARMRegisterInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.cpp updated: 1.31 -> 1.32
ARMInstrInfo.h updated: 1.12 -> 1.13
ARMLoadStoreOptimizer.cpp updated: 1.12 -> 1.13
ARMRegisterInfo.cpp updated: 1.96 -> 1.97
---
Log message:

Add missing const qualifiers.

---
Diffs of the changes:  (+24 -19)

 ARMInstrInfo.cpp          |   20 +++++++++++---------
 ARMInstrInfo.h            |   12 +++++++-----
 ARMLoadStoreOptimizer.cpp |    5 +++--
 ARMRegisterInfo.cpp       |    6 +++---
 4 files changed, 24 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.31 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.32
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.31	Wed May 23 02:22:05 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp	Tue May 29 13:42:18 2007
@@ -431,13 +431,13 @@
   return false;
 }
 
-bool ARMInstrInfo::isPredicated(MachineInstr *MI) const {
-  MachineOperand *PMO = MI->findFirstPredOperand();
-  return PMO && PMO->getImmedValue() != ARMCC::AL;
+bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
+  int PIdx = MI->findFirstPredOperandIdx();
+  return PIdx != -1 && MI->getOperand(PIdx).getImmedValue() != ARMCC::AL;
 }
 
 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
-                                      std::vector<MachineOperand> &Pred) const {
+                                const std::vector<MachineOperand> &Pred) const {
   unsigned Opc = MI->getOpcode();
   if (Opc == ARM::B || Opc == ARM::tB) {
     MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
@@ -445,16 +445,18 @@
     return true;
   }
 
-  MachineOperand *PMO = MI->findFirstPredOperand();
-  if (PMO) {
-    PMO->setImm(Pred[0].getImmedValue());
+  int PIdx = MI->findFirstPredOperandIdx();
+  if (PIdx != -1) {
+    MachineOperand &PMO = MI->getOperand(PIdx);
+    PMO.setImm(Pred[0].getImmedValue());
     return true;
   }
   return false;
 }
 
-bool ARMInstrInfo::SubsumesPredicate(std::vector<MachineOperand> &Pred1,
-                                     std::vector<MachineOperand> &Pred2) const{
+bool
+ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
+                                const std::vector<MachineOperand> &Pred2) const{
   if (Pred1.size() > 1 || Pred2.size() > 1)
     return false;
 


Index: llvm/lib/Target/ARM/ARMInstrInfo.h
diff -u llvm/lib/Target/ARM/ARMInstrInfo.h:1.12 llvm/lib/Target/ARM/ARMInstrInfo.h:1.13
--- llvm/lib/Target/ARM/ARMInstrInfo.h:1.12	Wed May 23 02:22:05 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.h	Tue May 29 13:42:18 2007
@@ -104,13 +104,15 @@
   virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
 
   // Predication support.
-  virtual bool isPredicated(MachineInstr *MI) const;
+  virtual bool isPredicated(const MachineInstr *MI) const;
 
-  virtual bool PredicateInstruction(MachineInstr *MI,
-                                    std::vector<MachineOperand> &Pred) const;
+  virtual
+  bool PredicateInstruction(MachineInstr *MI,
+                            const std::vector<MachineOperand> &Pred) const;
 
-  virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1,
-                                 std::vector<MachineOperand> &Pred1) const;
+  virtual
+  bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
+                         const std::vector<MachineOperand> &Pred1) const;
 };
 
   // Utility routines


Index: llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
diff -u llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.12 llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.13
--- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp:1.12	Mon May 14 20:29:07 2007
+++ llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp	Tue May 29 13:42:18 2007
@@ -245,8 +245,9 @@
 /// getInstrPredicate - If instruction is predicated, returns its predicate
 /// condition, otherwise returns AL.
 static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI) {
-  MachineOperand *PredMO = MI->findFirstPredOperand();
-  return PredMO ? (ARMCC::CondCodes)PredMO->getImmedValue() : ARMCC::AL;
+  int PIdx = MI->findFirstPredOperandIdx();
+  return PIdx == -1 ? ARMCC::AL
+                    : (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
 }
 
 static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.96 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.97
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.96	Mon May 14 20:29:07 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Tue May 29 13:42:18 2007
@@ -1009,9 +1009,9 @@
     if (ScratchReg == 0)
       // No register is "free". Scavenge a register.
       ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
-    MachineOperand *MO = MI.findFirstPredOperand();
-    ARMCC::CondCodes Pred = MO ?
-      (ARMCC::CondCodes)MO->getImmedValue() : ARMCC::AL;
+    int PIdx = MI.findFirstPredOperandIdx();
+    ARMCC::CondCodes Pred = (PIdx == -1)
+      ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
     emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, Pred,
                             isSub ? -Offset : Offset, TII);
     MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);