[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.103 -> 1.104
---
Log message:

Mark calls non-predicable for now. Need to ensure it's the last instruction in the if-converted block or make sure it preserve condition code.

---
Diffs of the changes:  (+8 -8)

 ARMInstrInfo.td |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.103 llvm/lib/Target/ARM/ARMInstrInfo.td:1.104
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.103	Wed May 16 15:50:01 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Thu May 17 20:53:54 2007
@@ -575,17 +575,17 @@
 let isCall = 1, noResults = 1, 
   Defs = [R0, R1, R2, R3, R12, LR,
           D0, D1, D2, D3, D4, D5, D6, D7] in {
-  def BL  : AXI<(ops i32imm:$func, pred:$p, variable_ops),
-                "bl$p ${func:call}",
+  def BL  : AXI<(ops i32imm:$func, variable_ops),
+                "bl ${func:call}",
                 [(ARMcall tglobaladdr:$func)]>;
   // ARMv5T and above
-  def BLX : AXI<(ops GPR:$dst, pred:$p, variable_ops),
-                "blx$p $dst",
+  def BLX : AXI<(ops GPR:$dst, variable_ops),
+                "blx $dst",
                 [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
   let Uses = [LR] in {
     // ARMv4T
-    def BX : AXIx2<(ops GPR:$dst, pred:$p, variable_ops),
-                  "mov$p lr, pc\n\tbx$p $dst",
+    def BX : AXIx2<(ops GPR:$dst, variable_ops),
+                  "mov lr, pc\n\tbx $dst",
                   [(ARMcall_nolink GPR:$dst)]>;
   }
 }
@@ -1110,8 +1110,8 @@
 // __aeabi_read_tp preserves the registers r1-r3.
 let isCall = 1,
   Defs = [R0, R12, LR] in {
-  def TPsoft : AI<(ops),
-               "bl", " __aeabi_read_tp",
+  def TPsoft : AXI<(ops),
+               "bl __aeabi_read_tp",
                [(set R0, ARMthread_pointer)]>;
 }