[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp

[Christopher Lamb]

Hi Nate,

Could you look into the possibility of re-using the sub/super  
register support that Evan recently added? This may prevent much  
duplication of information in the RegisterInfo.td, especially for  
targets with vector registers that have many subregisters.

I believe that sub/super register generator unions the set of sub/ 
super registers in a deterministic fashion and produces the necessary  
tables in the RegisterInfo.inc already. The only thing is that this  
would make the sub register index implicit in the ordering of the sub  
register list in the RegisterInfo.td.

Also, would it be possible to emit the information gathered as table  
lookups rather than a massive two level switch statement? I believe  
all the information to get the necessary mappings should be available.

--
Christopher Lamb


On May 1, 2007, at 12:57 AM, Nate Begeman wrote:

>
>
> Changes in directory llvm/utils/TableGen:
>
> RegisterInfoEmitter.cpp updated: 1.52 -> 1.53
> ---
> Log message:
>
> llvm bug #1350, parts 1, 2, and 3.
>
>
> ---
> Diffs of the changes:  (+36 -0)
>
>  RegisterInfoEmitter.cpp |   36 ++++++++++++++++++++++++++++++++++++
>  1 files changed, 36 insertions(+)
>
>
> Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
> diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52 llvm/utils/ 
> TableGen/RegisterInfoEmitter.cpp:1.53
> --- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52	Fri Apr 20  
> 19:55:29 2007
> +++ llvm/utils/TableGen/RegisterInfoEmitter.cpp	Tue May  1 00:57:02  
> 2007
> @@ -61,6 +61,7 @@
>       << "  " << ClassName
>       << "(int CallFrameSetupOpcode = -1, int  
> CallFrameDestroyOpcode = -1);\n"
>       << "  int getDwarfRegNum(unsigned RegNum) const;\n"
> +     << "  unsigned getSubReg(unsigned RegNo, unsigned Index)  
> const;\n"
>       << "};\n\n";
>
>    const std::vector<CodeGenRegisterClass> &RegisterClasses =
> @@ -322,6 +323,7 @@
>    std::map<Record*, std::set<Record*> > RegisterSubRegs;
>    std::map<Record*, std::set<Record*> > RegisterSuperRegs;
>    std::map<Record*, std::set<Record*> > RegisterAliases;
> +  std::map<Record*, std::vector<std::pair<int, Record*> > >  
> SubRegVectors;
>    const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
>
>    for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
> @@ -441,6 +443,40 @@
>
>    std::string ClassName = Target.getName() + "GenRegisterInfo";
>
> +  // Calculate the mapping of subregister+index pairs to physical  
> registers.
> +  std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions 
> ("SubRegSet");
> +  for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
> +    int subRegIndex = SubRegs[i]->getValueAsInt("index");
> +    std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs 
> ("From");
> +    std::vector<Record*> To   = SubRegs[i]->getValueAsListOfDefs 
> ("To");
> +
> +    assert((From.size() == To.size()) &&
> +           "SubRegSet has mismatched from/to size");
> +
> +    // For each entry in from/to vectors, insert the to register  
> at index
> +    for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
> +      SubRegVectors[From[ii]].push_back(std::make_pair 
> (subRegIndex, To[ii]));
> +  }
> +
> +  // Emit the subregister + index mapping function based on the  
> information
> +  // calculated above.
> +  OS << "unsigned " << ClassName
> +     << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
> +     << "  switch (RegNo) {\n"
> +     << "  default: abort(); break;\n";
> +  for (std::map<Record*, std::vector<std::pair<int, Record*> >  
> >::iterator
> +        I = SubRegVectors.begin(), E = SubRegVectors.end(); I !=  
> E; ++I) {
> +    OS << "  case " << getQualifiedName(I->first) << ":\n";
> +    OS << "    switch (Index) {\n";
> +    OS << "    default: abort(); break;\n";
> +    for (unsigned i = 0, e = I->second.size(); i != e; ++i)
> +      OS << "    case " << (I->second)[i].first << ": return "
> +         << getQualifiedName((I->second)[i].second) << ";\n";
> +    OS << "    }; break;\n";
> +  }
> +  OS << "  };\n";
> +  OS << "}\n\n";
> +
>    // Emit the constructor of the class...
>    OS << ClassName << "::" << ClassName
>       << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
>
>
>
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