[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp RegAllocLinearScan.cpp RegAllocLocal.cpp RegAllocSimple.cpp VirtRegMap.cpp
Evan Cheng
evan.cheng at apple.com
Wed Apr 25 15:12:06 PDT 2007
Changes in directory llvm/lib/CodeGen:
PrologEpilogInserter.cpp updated: 1.81 -> 1.82
RegAllocLinearScan.cpp updated: 1.144 -> 1.145
RegAllocLocal.cpp updated: 1.101 -> 1.102
RegAllocSimple.cpp updated: 1.82 -> 1.83
VirtRegMap.cpp updated: 1.109 -> 1.110
---
Log message:
Match MachineFunction::UsedPhysRegs changes.
---
Diffs of the changes: (+25 -48)
PrologEpilogInserter.cpp | 5 ++---
RegAllocLinearScan.cpp | 7 +------
RegAllocLocal.cpp | 21 ++++++++-------------
RegAllocSimple.cpp | 9 ++-------
VirtRegMap.cpp | 31 ++++++++++++-------------------
5 files changed, 25 insertions(+), 48 deletions(-)
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.81 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.82
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.81 Tue Apr 24 23:28:40 2007
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Wed Apr 25 17:11:48 2007
@@ -156,19 +156,18 @@
// Now figure out which *callee saved* registers are modified by the current
// function, thus needing to be saved and restored in the prolog/epilog.
//
- const bool *PhysRegsUsed = Fn.getUsedPhysregs();
const TargetRegisterClass* const *CSRegClasses =
RegInfo->getCalleeSavedRegClasses();
std::vector<CalleeSavedInfo> CSI;
for (unsigned i = 0; CSRegs[i]; ++i) {
unsigned Reg = CSRegs[i];
- if (PhysRegsUsed[Reg]) {
+ if (Fn.isPhysRegUsed(Reg)) {
// If the reg is modified, save it!
CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
} else {
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) { // Check alias registers too.
- if (PhysRegsUsed[*AliasSet]) {
+ if (Fn.isPhysRegUsed(*AliasSet)) {
CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
break;
}
Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.144 llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.145
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.144 Wed Apr 25 02:18:20 2007
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Wed Apr 25 17:11:48 2007
@@ -61,7 +61,6 @@
const TargetMachine* tm_;
const MRegisterInfo* mri_;
LiveIntervals* li_;
- bool *PhysRegsUsed;
/// handled_ - Intervals are added to the handled_ set in the order of their
/// start value. This is uses for backtracking.
@@ -194,10 +193,6 @@
if (RelatedRegClasses.empty())
ComputeRelatedRegClasses();
- PhysRegsUsed = new bool[mri_->getNumRegs()];
- std::fill(PhysRegsUsed, PhysRegsUsed+mri_->getNumRegs(), false);
- fn.setUsedPhysRegs(PhysRegsUsed);
-
if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_));
vrm_.reset(new VirtRegMap(*mf_));
if (!spiller_.get()) spiller_.reset(createSpiller());
@@ -231,7 +226,7 @@
for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
if (MRegisterInfo::isPhysicalRegister(i->second.reg)) {
- PhysRegsUsed[i->second.reg] = true;
+ mf_->setPhysRegUsed(i->second.reg);
fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
} else
unhandled_.push(&i->second);
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.101 llvm/lib/CodeGen/RegAllocLocal.cpp:1.102
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.101 Wed Feb 14 23:59:24 2007
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Wed Apr 25 17:11:48 2007
@@ -47,7 +47,6 @@
MachineFunction *MF;
const MRegisterInfo *RegInfo;
LiveVariables *LV;
- bool *PhysRegsEverUsed;
// StackSlotForVirtReg - Maps virtual regs to the frame index where these
// values are spilled.
@@ -511,7 +510,7 @@
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
- PhysRegsEverUsed[PhysReg] = true;
+ MF->setPhysRegUsed(PhysReg);
MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
return MI;
}
@@ -532,7 +531,7 @@
for (MachineFunction::livein_iterator I = MF->livein_begin(),
E = MF->livein_end(); I != E; ++I) {
unsigned Reg = I->first;
- PhysRegsEverUsed[Reg] = true;
+ MF->setPhysRegUsed(Reg);
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
@@ -540,7 +539,7 @@
if (PhysRegsUsed[*AliasSet] != -2) {
PhysRegsUseOrder.push_back(*AliasSet);
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
- PhysRegsEverUsed[*AliasSet] = true;
+ MF->setPhysRegUsed(*AliasSet);
}
}
}
@@ -630,7 +629,7 @@
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
- PhysRegsEverUsed[Reg] = true;
+ MF->setPhysRegUsed(Reg);
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
@@ -639,7 +638,7 @@
if (PhysRegsUsed[*AliasSet] != -2) {
PhysRegsUseOrder.push_back(*AliasSet);
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
- PhysRegsEverUsed[*AliasSet] = true;
+ MF->setPhysRegUsed(*AliasSet);
}
}
}
@@ -656,7 +655,7 @@
PhysRegsUseOrder.push_back(Reg);
PhysRegsUsed[Reg] = 0; // It is free and reserved now
}
- PhysRegsEverUsed[Reg] = true;
+ MF->setPhysRegUsed(Reg);
for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
*AliasSet; ++AliasSet) {
@@ -665,7 +664,7 @@
PhysRegsUseOrder.push_back(*AliasSet);
PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
}
- PhysRegsEverUsed[*AliasSet] = true;
+ MF->setPhysRegUsed(*AliasSet);
}
}
}
@@ -693,7 +692,7 @@
// If DestVirtReg already has a value, use it.
if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
DestPhysReg = getReg(MBB, MI, DestVirtReg);
- PhysRegsEverUsed[DestPhysReg] = true;
+ MF->setPhysRegUsed(DestPhysReg);
markVirtRegModified(DestVirtReg);
MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
}
@@ -779,10 +778,6 @@
RegInfo = TM->getRegisterInfo();
LV = &getAnalysis<LiveVariables>();
- PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
- std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
- Fn.setUsedPhysRegs(PhysRegsEverUsed);
-
PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
// At various places we want to efficiently check to see whether a register
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.82 llvm/lib/CodeGen/RegAllocSimple.cpp:1.83
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.82 Tue Dec 19 16:41:21 2006
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Wed Apr 25 17:11:48 2007
@@ -41,7 +41,6 @@
MachineFunction *MF;
const TargetMachine *TM;
const MRegisterInfo *RegInfo;
- bool *PhysRegsEverUsed;
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
@@ -126,7 +125,7 @@
unsigned PhysReg = *(RI+regIdx);
if (!RegsUsed[PhysReg]) {
- PhysRegsEverUsed[PhysReg] = true;
+ MF->setPhysRegUsed(PhysReg);
return PhysReg;
}
}
@@ -178,7 +177,7 @@
if (Desc.ImplicitDefs) {
for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
RegsUsed[*Regs] = true;
- PhysRegsEverUsed[*Regs] = true;
+ MF->setPhysRegUsed(*Regs);
}
}
@@ -236,10 +235,6 @@
TM = &MF->getTarget();
RegInfo = TM->getRegisterInfo();
- PhysRegsEverUsed = new bool[RegInfo->getNumRegs()];
- std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false);
- Fn.setUsedPhysRegs(PhysRegsEverUsed);
-
// Loop over all of the basic blocks, eliminating virtual register references
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB)
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.109 llvm/lib/CodeGen/VirtRegMap.cpp:1.110
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.109 Wed Apr 4 02:40:01 2007
+++ llvm/lib/CodeGen/VirtRegMap.cpp Wed Apr 25 17:11:48 2007
@@ -174,7 +174,6 @@
DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
const TargetMachine &TM = MF.getTarget();
const MRegisterInfo &MRI = *TM.getRegisterInfo();
- bool *PhysRegsUsed = MF.getUsedPhysregs();
// LoadedRegs - Keep track of which vregs are loaded, so that we only load
// each vreg once (in the case where a spilled vreg is used by multiple
@@ -214,10 +213,10 @@
++NumStores;
}
}
- PhysRegsUsed[PhysReg] = true;
+ MF.setPhysRegUsed(PhysReg);
MI.getOperand(i).setReg(PhysReg);
} else {
- PhysRegsUsed[MO.getReg()] = true;
+ MF.setPhysRegUsed(MO.getReg());
}
}
@@ -648,8 +647,7 @@
// same stack slot, the original store is deleted.
std::map<int, MachineInstr*> MaybeDeadStores;
- bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
-
+ MachineFunction &MF = *MBB.getParent();
for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
MII != E; ) {
MachineInstr &MI = *MII;
@@ -688,7 +686,7 @@
const unsigned *ImpDef = TID->ImplicitDefs;
if (ImpDef) {
for ( ; *ImpDef; ++ImpDef) {
- PhysRegsUsed[*ImpDef] = true;
+ MF.setPhysRegUsed(*ImpDef);
ReusedOperands.markClobbered(*ImpDef);
Spills.ClobberPhysReg(*ImpDef);
}
@@ -703,7 +701,7 @@
if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
// Ignore physregs for spilling, but remember that it is used by this
// function.
- PhysRegsUsed[MO.getReg()] = true;
+ MF.setPhysRegUsed(MO.getReg());
ReusedOperands.markClobbered(MO.getReg());
continue;
}
@@ -715,7 +713,7 @@
if (!VRM.hasStackSlot(VirtReg)) {
// This virtual register was assigned a physreg!
unsigned Phys = VRM.getPhys(VirtReg);
- PhysRegsUsed[Phys] = true;
+ MF.setPhysRegUsed(Phys);
if (MO.isDef())
ReusedOperands.markClobbered(Phys);
MI.getOperand(i).setReg(Phys);
@@ -842,10 +840,8 @@
continue;
}
- const TargetRegisterClass* RC =
- MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
-
- PhysRegsUsed[DesignatedReg] = true;
+ const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
+ MF.setPhysRegUsed(DesignatedReg);
ReusedOperands.markClobbered(DesignatedReg);
MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
@@ -883,8 +879,7 @@
// Otherwise, reload it and remember that we have it.
PhysReg = VRM.getPhys(VirtReg);
assert(PhysReg && "Must map virtreg to physreg!");
- const TargetRegisterClass* RC =
- MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
+ const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
// Note that, if we reused a register for a previous operand, the
// register we want to reload into might not actually be
@@ -894,7 +889,7 @@
PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Spills, MaybeDeadStores);
- PhysRegsUsed[PhysReg] = true;
+ MF.setPhysRegUsed(PhysReg);
ReusedOperands.markClobbered(PhysReg);
if (doReMat) {
MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
@@ -947,7 +942,6 @@
MachineInstr *SSMI = NULL;
if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, SSMI)) {
DOUT << "Promoted Load To Copy: " << MI;
- MachineFunction &MF = *MBB.getParent();
if (DestReg != InReg) {
MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
MF.getSSARegMap()->getRegClass(VirtReg));
@@ -1081,8 +1075,7 @@
// The only vregs left are stack slot definitions.
int StackSlot = VRM.getStackSlot(VirtReg);
- const TargetRegisterClass *RC =
- MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
+ const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(VirtReg);
// If this def is part of a two-address operand, make sure to execute
// the store from the correct physical register.
@@ -1100,7 +1093,7 @@
}
}
- PhysRegsUsed[PhysReg] = true;
+ MF.setPhysRegUsed(PhysReg);
ReusedOperands.markClobbered(PhysReg);
MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
DOUT << "Store:\t" << *next(MII);
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