[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.292 -> 1.293
---
Log message:

allow SRL to simplify its operands, as it doesn't demand all bits as input.


---
Diffs of the changes:  (+7 -1)

 DAGCombiner.cpp |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.292 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.293
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.292	Tue Apr 17 22:05:22 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Tue Apr 17 22:06:49 2007
@@ -1728,7 +1728,7 @@
   // if (shl x, c) is known to be zero, return 0
   if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
     return DAG.getConstant(0, VT);
-  if (SimplifyDemandedBits(SDOperand(N, 0)))
+  if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
     return SDOperand(N, 0);
   // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
   if (N1C && N0.getOpcode() == ISD::SHL && 
@@ -1907,6 +1907,12 @@
       return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
     }
   }
+  
+  // fold operands of srl based on knowledge that the low bits are not
+  // demanded.
+  if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
+    return SDOperand(N, 0);
+  
   return SDOperand();
 }