[llvm-commits] CVS: llvm/lib/Target/MRegisterInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target:

MRegisterInfo.cpp updated: 1.23 -> 1.24
---
Log message:

Oops. Didn't mean to check in a quick hack.

---
Diffs of the changes:  (+16 -8)

 MRegisterInfo.cpp |   24 ++++++++++++++++--------
 1 files changed, 16 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/MRegisterInfo.cpp
diff -u llvm/lib/Target/MRegisterInfo.cpp:1.23 llvm/lib/Target/MRegisterInfo.cpp:1.24
--- llvm/lib/Target/MRegisterInfo.cpp:1.23	Tue Apr 17 15:23:34 2007
+++ llvm/lib/Target/MRegisterInfo.cpp	Tue Apr 17 18:33:39 2007
@@ -34,18 +34,26 @@
 
 MRegisterInfo::~MRegisterInfo() {}
 
+/// getAllocatableSetForRC - Toggle the bits that represent allocatable
+/// registers for the specific register class.
+static void getAllocatableSetForRC(MachineFunction &MF,
+                                   const TargetRegisterClass *RC, BitVector &R){  
+  for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
+         E = RC->allocation_order_end(MF); I != E; ++I)
+    R.set(*I);
+}
+
 BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
                                            const TargetRegisterClass *RC) const {
   BitVector Allocatable(NumRegs);
-  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
-         E = regclass_end(); I != E; ++I) {
-    const TargetRegisterClass *TRC = *I;
-    if (RC && TRC != RC)
-      continue;
-    for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(MF),
-           E = TRC->allocation_order_end(MF); I != E; ++I)
-      Allocatable.set(*I);
+  if (RC) {
+    getAllocatableSetForRC(MF, RC, Allocatable);
+    return Allocatable;
   }
+
+  for (MRegisterInfo::regclass_iterator I = regclass_begin(),
+         E = regclass_end(); I != E; ++I)
+    getAllocatableSetForRC(MF, *I, Allocatable);
   return Allocatable;
 }