[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaLLRP.cpp AlphaRegisterInfo.cpp
Anton Korobeynikov
asl at math.spbu.ru
Mon Apr 16 11:11:40 PDT 2007
Changes in directory llvm/lib/Target/Alpha:
AlphaAsmPrinter.cpp updated: 1.63 -> 1.64
AlphaISelDAGToDAG.cpp updated: 1.68 -> 1.69
AlphaISelLowering.cpp updated: 1.85 -> 1.86
AlphaLLRP.cpp updated: 1.7 -> 1.8
AlphaRegisterInfo.cpp updated: 1.64 -> 1.65
---
Log message:
Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.
---
Diffs of the changes: (+207 -205)
AlphaAsmPrinter.cpp | 16 ++--
AlphaISelDAGToDAG.cpp | 108 ++++++++++++++--------------
AlphaISelLowering.cpp | 79 ++++++++++----------
AlphaLLRP.cpp | 189 +++++++++++++++++++++++++-------------------------
AlphaRegisterInfo.cpp | 20 ++---
5 files changed, 207 insertions(+), 205 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.63 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.64
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.63 Tue Feb 13 17:41:16 2007
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Mon Apr 16 13:10:22 2007
@@ -53,9 +53,9 @@
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode);
bool PrintAsmMemoryOperand(const MachineInstr *MI,
- unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode);
+ unsigned OpNo,
+ unsigned AsmVariant,
+ const char *ExtraCode);
};
} // end of anonymous namespace
@@ -278,16 +278,16 @@
/// PrintAsmOperand - Print out an operand for an inline asm expression.
///
bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode) {
+ unsigned AsmVariant,
+ const char *ExtraCode) {
printOperand(MI, OpNo);
return false;
}
bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
- unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode) {
+ unsigned OpNo,
+ unsigned AsmVariant,
+ const char *ExtraCode) {
if (ExtraCode && ExtraCode[0])
return true; // Unknown modifier.
O << "0(";
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.68 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.69
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.68 Wed Jan 24 15:09:16 2007
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Mon Apr 16 13:10:22 2007
@@ -50,7 +50,7 @@
static int64_t get_ldah16(int64_t x) {
int64_t y = x / IMM_MULT;
if (x % IMM_MULT > IMM_HIGH)
- ++y;
+ ++y;
return y;
}
@@ -145,7 +145,7 @@
public:
AlphaDAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(AlphaLowering),
- AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
+ AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
{}
/// getI64Imm - Return a target constant with the specified value, of type
@@ -177,7 +177,7 @@
default: return true;
case 'm': // memory
Op0 = Op;
- AddToISelQueue(Op0);
+ AddToISelQueue(Op0);
break;
}
@@ -203,7 +203,7 @@
MachineFunction* MF = BB->getParent();
unsigned GP = 0;
for(MachineFunction::livein_iterator ii = MF->livein_begin(),
- ee = MF->livein_end(); ii != ee; ++ii)
+ ee = MF->livein_end(); ii != ee; ++ii)
if (ii->first == Alpha::R29) {
GP = ii->second;
break;
@@ -219,7 +219,7 @@
MachineFunction* MF = BB->getParent();
unsigned RA = 0;
for(MachineFunction::livein_iterator ii = MF->livein_begin(),
- ee = MF->livein_end(); ii != ee; ++ii)
+ ee = MF->livein_end(); ii != ee; ++ii)
if (ii->first == Alpha::R26) {
RA = ii->second;
break;
@@ -283,16 +283,16 @@
AddToISelQueue(N1);
AddToISelQueue(N2);
Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
- SDOperand(0,0));
+ SDOperand(0,0));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
- Chain.getValue(1));
+ Chain.getValue(1));
Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
- Chain.getValue(1));
+ Chain.getValue(1));
SDNode *CNode =
CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
Chain, Chain.getValue(1));
Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
- SDOperand(CNode, 1));
+ SDOperand(CNode, 1));
return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
}
@@ -316,11 +316,11 @@
int64_t val = (int64_t)uval;
int32_t val32 = (int32_t)val;
if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
- val >= IMM_LOW + IMM_LOW * IMM_MULT)
+ val >= IMM_LOW + IMM_LOW * IMM_MULT)
break; //(LDAH (LDA))
if ((uval >> 32) == 0 && //empty upper bits
- val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
- // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
+ val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
+ // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
break; //(zext (LDAH (LDA)))
//Else use the constant pool
ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
@@ -328,7 +328,7 @@
SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
getGlobalBaseReg());
return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
- CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
+ CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
}
case ISD::TargetConstantFP: {
ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
@@ -358,21 +358,21 @@
switch(CC) {
default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
- Opc = Alpha::CMPTEQ; break;
+ Opc = Alpha::CMPTEQ; break;
case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
- Opc = Alpha::CMPTLT; break;
+ Opc = Alpha::CMPTLT; break;
case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
- Opc = Alpha::CMPTLE; break;
+ Opc = Alpha::CMPTLE; break;
case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
- Opc = Alpha::CMPTLT; rev = true; break;
+ Opc = Alpha::CMPTLT; rev = true; break;
case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
- Opc = Alpha::CMPTLE; rev = true; break;
+ Opc = Alpha::CMPTLE; rev = true; break;
case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
- Opc = Alpha::CMPTEQ; inv = true; break;
+ Opc = Alpha::CMPTEQ; inv = true; break;
case ISD::SETO:
- Opc = Alpha::CMPTUN; inv = true; break;
+ Opc = Alpha::CMPTUN; inv = true; break;
case ISD::SETUO:
- Opc = Alpha::CMPTUN; break;
+ Opc = Alpha::CMPTUN; break;
};
SDOperand tmp1 = N->getOperand(rev?1:0);
SDOperand tmp2 = N->getOperand(rev?0:1);
@@ -385,12 +385,13 @@
switch(CC) {
case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
- {
- SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64, tmp1, tmp2);
- cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
- SDOperand(cmp2, 0), SDOperand(cmp, 0));
- break;
- }
+ {
+ SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
+ tmp1, tmp2);
+ cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
+ SDOperand(cmp2, 0), SDOperand(cmp, 0));
+ break;
+ }
default: break;
}
@@ -403,8 +404,8 @@
case ISD::SELECT:
if (MVT::isFloatingPoint(N->getValueType(0)) &&
- (N->getOperand(0).getOpcode() != ISD::SETCC ||
- !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
+ (N->getOperand(0).getOpcode() != ISD::SETCC ||
+ !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
//This should be the condition not covered by the Patterns
//FIXME: Don't have SelectCode die, but rather return something testable
// so that things like this can be caught in fall though code
@@ -427,32 +428,31 @@
ConstantSDNode* SC = NULL;
ConstantSDNode* MC = NULL;
if (N->getOperand(0).getOpcode() == ISD::SRL &&
- (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
- (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1))))
- {
- uint64_t sval = SC->getValue();
- uint64_t mval = MC->getValue();
- // If the result is a zap, let the autogened stuff handle it.
- if (get_zapImm(N->getOperand(0), mval))
- break;
- // given mask X, and shift S, we want to see if there is any zap in the
- // mask if we play around with the botton S bits
- uint64_t dontcare = (~0ULL) >> (64 - sval);
- uint64_t mask = mval << sval;
-
- if (get_zapImm(mask | dontcare))
- mask = mask | dontcare;
-
- if (get_zapImm(mask)) {
- AddToISelQueue(N->getOperand(0).getOperand(0));
- SDOperand Z =
- SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
- N->getOperand(0).getOperand(0),
- getI64Imm(get_zapImm(mask))), 0);
- return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
- getI64Imm(sval));
- }
+ (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
+ (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
+ uint64_t sval = SC->getValue();
+ uint64_t mval = MC->getValue();
+ // If the result is a zap, let the autogened stuff handle it.
+ if (get_zapImm(N->getOperand(0), mval))
+ break;
+ // given mask X, and shift S, we want to see if there is any zap in the
+ // mask if we play around with the botton S bits
+ uint64_t dontcare = (~0ULL) >> (64 - sval);
+ uint64_t mask = mval << sval;
+
+ if (get_zapImm(mask | dontcare))
+ mask = mask | dontcare;
+
+ if (get_zapImm(mask)) {
+ AddToISelQueue(N->getOperand(0).getOperand(0));
+ SDOperand Z =
+ SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
+ N->getOperand(0).getOperand(0),
+ getI64Imm(get_zapImm(mask))), 0);
+ return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
+ getI64Imm(sval));
}
+ }
break;
}
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.85 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.86
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.85 Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Mon Apr 16 13:10:22 2007
@@ -172,7 +172,7 @@
SDOperand Zero = DAG.getConstant(0, PtrVT);
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
return Lo;
}
@@ -197,8 +197,8 @@
// //#define SP $30
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
- int &VarArgsBase,
- int &VarArgsOffset) {
+ int &VarArgsBase,
+ int &VarArgsOffset) {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
std::vector<SDOperand> ArgValues;
@@ -224,17 +224,17 @@
abort();
case MVT::f64:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
- &Alpha::F8RCRegClass);
+ &Alpha::F8RCRegClass);
ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
break;
case MVT::f32:
args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
- &Alpha::F4RCRegClass);
+ &Alpha::F4RCRegClass);
ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
break;
case MVT::i64:
args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
- &Alpha::GPRCRegClass);
+ &Alpha::GPRCRegClass);
ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
break;
}
@@ -286,9 +286,9 @@
static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
- DAG.getNode(AlphaISD::GlobalRetAddr,
- MVT::i64),
- SDOperand());
+ DAG.getNode(AlphaISD::GlobalRetAddr,
+ MVT::i64),
+ SDOperand());
switch (Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
@@ -306,7 +306,7 @@
ArgReg = Alpha::F0;
}
Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
- if(DAG.getMachineFunction().liveout_empty())
+ if (DAG.getMachineFunction().liveout_empty())
DAG.getMachineFunction().addLiveOut(ArgReg);
break;
}
@@ -387,8 +387,8 @@
switch (Op.getOpcode()) {
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
- VarArgsBase,
- VarArgsOffset);
+ VarArgsBase,
+ VarArgsOffset);
case ISD::RET: return LowerRET(Op,DAG);
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
@@ -420,7 +420,7 @@
SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
return Lo;
}
@@ -432,18 +432,18 @@
// if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) {
if (GV->hasInternalLinkage()) {
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
return Lo;
} else
return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
}
case ISD::ExternalSymbol: {
return DAG.getNode(AlphaISD::RelLit, MVT::i64,
- DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
- ->getSymbol(), MVT::i64),
- DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
+ DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
+ ->getSymbol(), MVT::i64),
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
}
case ISD::UREM:
@@ -452,8 +452,8 @@
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
MVT::ValueType VT = Op.Val->getValueType(0);
SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
- BuildUDIV(Op.Val, DAG, NULL) :
- BuildSDIV(Op.Val, DAG, NULL);
+ BuildUDIV(Op.Val, DAG, NULL) :
+ BuildSDIV(Op.Val, DAG, NULL);
Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
return Tmp1;
@@ -463,10 +463,10 @@
case ISD::UDIV:
if (MVT::isInteger(Op.getValueType())) {
if (Op.getOperand(1).getOpcode() == ISD::Constant)
- return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
- : BuildUDIV(Op.Val, DAG, NULL);
+ return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
+ : BuildUDIV(Op.Val, DAG, NULL);
const char* opstr = 0;
- switch(Op.getOpcode()) {
+ switch (Op.getOpcode()) {
case ISD::UREM: opstr = "__remqu"; break;
case ISD::SREM: opstr = "__remq"; break;
case ISD::UDIV: opstr = "__divqu"; break;
@@ -591,29 +591,28 @@
default: break; // Unknown constriant letter
case 'f':
return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
- Alpha::F3 , Alpha::F4 , Alpha::F5 ,
- Alpha::F6 , Alpha::F7 , Alpha::F8 ,
- Alpha::F9 , Alpha::F10, Alpha::F11,
+ Alpha::F3 , Alpha::F4 , Alpha::F5 ,
+ Alpha::F6 , Alpha::F7 , Alpha::F8 ,
+ Alpha::F9 , Alpha::F10, Alpha::F11,
Alpha::F12, Alpha::F13, Alpha::F14,
- Alpha::F15, Alpha::F16, Alpha::F17,
- Alpha::F18, Alpha::F19, Alpha::F20,
- Alpha::F21, Alpha::F22, Alpha::F23,
+ Alpha::F15, Alpha::F16, Alpha::F17,
+ Alpha::F18, Alpha::F19, Alpha::F20,
+ Alpha::F21, Alpha::F22, Alpha::F23,
Alpha::F24, Alpha::F25, Alpha::F26,
- Alpha::F27, Alpha::F28, Alpha::F29,
- Alpha::F30, Alpha::F31, 0);
+ Alpha::F27, Alpha::F28, Alpha::F29,
+ Alpha::F30, Alpha::F31, 0);
case 'r':
return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
- Alpha::R3 , Alpha::R4 , Alpha::R5 ,
- Alpha::R6 , Alpha::R7 , Alpha::R8 ,
- Alpha::R9 , Alpha::R10, Alpha::R11,
+ Alpha::R3 , Alpha::R4 , Alpha::R5 ,
+ Alpha::R6 , Alpha::R7 , Alpha::R8 ,
+ Alpha::R9 , Alpha::R10, Alpha::R11,
Alpha::R12, Alpha::R13, Alpha::R14,
- Alpha::R15, Alpha::R16, Alpha::R17,
- Alpha::R18, Alpha::R19, Alpha::R20,
- Alpha::R21, Alpha::R22, Alpha::R23,
+ Alpha::R15, Alpha::R16, Alpha::R17,
+ Alpha::R18, Alpha::R19, Alpha::R20,
+ Alpha::R21, Alpha::R22, Alpha::R23,
Alpha::R24, Alpha::R25, Alpha::R26,
- Alpha::R27, Alpha::R28, Alpha::R29,
- Alpha::R30, Alpha::R31, 0);
-
+ Alpha::R27, Alpha::R28, Alpha::R29,
+ Alpha::R30, Alpha::R31, 0);
}
}
Index: llvm/lib/Target/Alpha/AlphaLLRP.cpp
diff -u llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.7 llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.8
--- llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.7 Tue Dec 19 16:59:25 2006
+++ llvm/lib/Target/Alpha/AlphaLLRP.cpp Mon Apr 16 13:10:22 2007
@@ -50,101 +50,104 @@
unsigned count = 0;
for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI) {
- MachineBasicBlock& MBB = *FI;
- bool ub = false;
- for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
- if (count%4 == 0)
- prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
- ++count;
- MachineInstr *MI = I++;
- switch (MI->getOpcode()) {
- case Alpha::LDQ: case Alpha::LDL:
- case Alpha::LDWU: case Alpha::LDBU:
- case Alpha::LDT: case Alpha::LDS:
- case Alpha::STQ: case Alpha::STL:
- case Alpha::STW: case Alpha::STB:
- case Alpha::STT: case Alpha::STS:
- if (MI->getOperand(2).getReg() == Alpha::R30) {
- if (prev[0]
- && prev[0]->getOperand(2).getReg() ==
- MI->getOperand(2).getReg()
- && prev[0]->getOperand(1).getImmedValue() ==
- MI->getOperand(1).getImmedValue()) {
- prev[0] = prev[1];
- prev[1] = prev[2];
- prev[2] = 0;
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- Changed = true; nopintro += 1;
- count += 1;
- } else if (prev[1]
- && prev[1]->getOperand(2).getReg() ==
- MI->getOperand(2).getReg()
- && prev[1]->getOperand(1).getImmedValue() ==
- MI->getOperand(1).getImmedValue()) {
- prev[0] = prev[2];
- prev[1] = prev[2] = 0;
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- Changed = true; nopintro += 2;
- count += 2;
- } else if (prev[2]
- && prev[2]->getOperand(2).getReg() ==
- MI->getOperand(2).getReg()
- && prev[2]->getOperand(1).getImmedValue() ==
- MI->getOperand(1).getImmedValue()) {
- prev[0] = prev[1] = prev[2] = 0;
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- Changed = true; nopintro += 3;
- count += 3;
- }
- prev[0] = prev[1];
- prev[1] = prev[2];
- prev[2] = MI;
- break;
- }
- prev[0] = prev[1];
- prev[1] = prev[2];
- prev[2] = 0;
- break;
- case Alpha::ALTENT:
- case Alpha::MEMLABEL:
- case Alpha::PCLABEL:
- case Alpha::IDEF_I:
- case Alpha::IDEF_F32:
- case Alpha::IDEF_F64:
- --count;
- break;
- case Alpha::BR:
- case Alpha::JMP:
- ub = true;
- //fall through
- default:
- prev[0] = prev[1];
- prev[1] = prev[2];
- prev[2] = 0;
- break;
- }
+ MachineBasicBlock& MBB = *FI;
+ bool ub = false;
+ for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
+ if (count%4 == 0)
+ prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
+ ++count;
+ MachineInstr *MI = I++;
+ switch (MI->getOpcode()) {
+ case Alpha::LDQ: case Alpha::LDL:
+ case Alpha::LDWU: case Alpha::LDBU:
+ case Alpha::LDT: case Alpha::LDS:
+ case Alpha::STQ: case Alpha::STL:
+ case Alpha::STW: case Alpha::STB:
+ case Alpha::STT: case Alpha::STS:
+ if (MI->getOperand(2).getReg() == Alpha::R30) {
+ if (prev[0]
+ && prev[0]->getOperand(2).getReg() ==
+ MI->getOperand(2).getReg()
+ && prev[0]->getOperand(1).getImmedValue() ==
+ MI->getOperand(1).getImmedValue()) {
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = 0;
+ BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+ .addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ Changed = true; nopintro += 1;
+ count += 1;
+ } else if (prev[1]
+ && prev[1]->getOperand(2).getReg() ==
+ MI->getOperand(2).getReg()
+ && prev[1]->getOperand(1).getImmedValue() ==
+ MI->getOperand(1).getImmedValue()) {
+ prev[0] = prev[2];
+ prev[1] = prev[2] = 0;
+ BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+ .addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
+ .addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ Changed = true; nopintro += 2;
+ count += 2;
+ } else if (prev[2]
+ && prev[2]->getOperand(2).getReg() ==
+ MI->getOperand(2).getReg()
+ && prev[2]->getOperand(1).getImmedValue() ==
+ MI->getOperand(1).getImmedValue()) {
+ prev[0] = prev[1] = prev[2] = 0;
+ BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ Changed = true; nopintro += 3;
+ count += 3;
+ }
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = MI;
+ break;
+ }
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = 0;
+ break;
+ case Alpha::ALTENT:
+ case Alpha::MEMLABEL:
+ case Alpha::PCLABEL:
+ case Alpha::IDEF_I:
+ case Alpha::IDEF_F32:
+ case Alpha::IDEF_F64:
+ --count;
+ break;
+ case Alpha::BR:
+ case Alpha::JMP:
+ ub = true;
+ //fall through
+ default:
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = 0;
+ break;
}
- if (ub || AlignAll) {
- //we can align stuff for free at this point
- while (count % 4) {
- BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
- .addReg(Alpha::R31).addReg(Alpha::R31);
- ++count;
- ++nopalign;
- prev[0] = prev[1];
- prev[1] = prev[2];
- prev[2] = 0;
- }
+ }
+ if (ub || AlignAll) {
+ //we can align stuff for free at this point
+ while (count % 4) {
+ BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
+ .addReg(Alpha::R31).addReg(Alpha::R31);
+ ++count;
+ ++nopalign;
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = 0;
}
+ }
}
return Changed;
}
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.64 llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.65
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp:1.64 Tue Mar 20 03:07:46 2007
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon Apr 16 13:10:22 2007
@@ -117,17 +117,17 @@
case Alpha::CPYST:
if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
if (OpNum == 0) { // move -> store
- unsigned InReg = MI->getOperand(1).getReg();
- Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
- ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
- NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
- .addReg(Alpha::F31);
+ unsigned InReg = MI->getOperand(1).getReg();
+ Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
+ ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
+ NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
} else { // load -> move
- unsigned OutReg = MI->getOperand(0).getReg();
- Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
- ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
- NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
- .addReg(Alpha::F31);
+ unsigned OutReg = MI->getOperand(0).getReg();
+ Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
+ ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
+ NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
+ .addReg(Alpha::F31);
}
}
break;
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