[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.407 -> 1.408
---
Log message:

implement CodeGen/X86/inline-asm-x-scalar.ll:test3


---
Diffs of the changes:  (+9 -2)

 SelectionDAGISel.cpp |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.407 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.408
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.407	Sun Apr  8 19:33:58 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Mon Apr  9 00:31:20 2007
@@ -2656,13 +2656,20 @@
       if (MVT::isVector(RegVT)) {
         assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector cast?");
         Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
-      } else if (MVT::isInteger(RegVT)) {
+      } else if (MVT::isInteger(RegVT) && MVT::isInteger(Val.getValueType())) {
         if (RegVT < ValueVT)
           Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
         else
           Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
-      } else
+      } else if (MVT::isFloatingPoint(RegVT) &&
+                 MVT::isFloatingPoint(Val.getValueType())) {
         Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
+      } else if (MVT::getSizeInBits(RegVT) == 
+                 MVT::getSizeInBits(Val.getValueType())) {
+        Val = DAG.getNode(ISD::BIT_CONVERT, RegVT, Val);
+      } else {
+        assert(0 && "Unknown mismatch!");
+      }
     }
     Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
     Flag = Chain.getValue(1);