[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Evan Cheng]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.279 -> 1.280
---
Log message:

Make sure SEXTLOAD of the specific type is supported on the target.

---
Diffs of the changes:  (+4 -0)

 DAGCombiner.cpp |    4 ++++
 1 files changed, 4 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.279 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.280
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.279	Fri Mar 23 15:55:21 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Fri Mar 23 17:13:36 2007
@@ -2272,9 +2272,13 @@
   MVT::ValueType VT = N->getValueType(0);
   MVT::ValueType EVT = N->getValueType(0);
 
+  // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
+  // extended to VT.
   if (Opc == ISD::SIGN_EXTEND_INREG) {
     ExtType = ISD::SEXTLOAD;
     EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+    if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
+      return SDOperand();
   }
 
   unsigned EVTBits = MVT::getSizeInBits(EVT);