[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.cpp X86InstrMMX.td X86RegisterInfo.cpp
Bill Wendling
isanbard at gmail.com
Thu Mar 8 14:09:32 PST 2007
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.364 -> 1.365
X86InstrInfo.cpp updated: 1.77 -> 1.78
X86InstrMMX.td updated: 1.17 -> 1.18
X86RegisterInfo.cpp updated: 1.206 -> 1.207
---
Log message:
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
moves, loads, etc. are recognized.
---
Diffs of the changes: (+73 -10)
X86ISelLowering.cpp | 23 ++++++++++++++---------
X86InstrInfo.cpp | 7 ++++++-
X86InstrMMX.td | 47 +++++++++++++++++++++++++++++++++++++++++++++++
X86RegisterInfo.cpp | 6 ++++++
4 files changed, 73 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.364 llvm/lib/Target/X86/X86ISelLowering.cpp:1.365
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.364 Wed Mar 7 10:25:09 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Mar 8 16:09:11 2007
@@ -326,15 +326,20 @@
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
- setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
- AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
- setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
- AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
- setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
-
- setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
- setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
+
+ setOperationAction(ISD::ADD, MVT::v8i8, Legal);
+ setOperationAction(ISD::ADD, MVT::v4i16, Legal);
+ setOperationAction(ISD::ADD, MVT::v2i32, Legal);
+
+ setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
+ AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v2i32);
+ setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
+ AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v2i32);
+ setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
+
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
+ setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
}
if (Subtarget->hasSSE1()) {
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.77 llvm/lib/Target/X86/X86InstrInfo.cpp:1.78
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.77 Fri Jan 26 08:34:51 2007
+++ llvm/lib/Target/X86/X86InstrInfo.cpp Thu Mar 8 16:09:11 2007
@@ -37,7 +37,8 @@
oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr ||
- oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr) {
+ oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr ||
+ oc == X86::MOVD64rr || oc == X86::MOVQ64rr) {
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
@@ -64,6 +65,8 @@
case X86::MOVSDrm:
case X86::MOVAPSrm:
case X86::MOVAPDrm:
+ case X86::MOVD64rm:
+ case X86::MOVQ64rm:
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
MI->getOperand(2).getImmedValue() == 1 &&
@@ -92,6 +95,8 @@
case X86::MOVSDmr:
case X86::MOVAPSmr:
case X86::MOVAPDmr:
+ case X86::MOVD64mr:
+ case X86::MOVQ64mr:
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
MI->getOperand(1).getImmedValue() == 1 &&
Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.17 llvm/lib/Target/X86/X86InstrMMX.td:1.18
--- llvm/lib/Target/X86/X86InstrMMX.td:1.17 Wed Mar 7 12:23:09 2007
+++ llvm/lib/Target/X86/X86InstrMMX.td Thu Mar 8 16:09:11 2007
@@ -45,6 +45,42 @@
def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
//===----------------------------------------------------------------------===//
+// MMX Multiclasses
+//===----------------------------------------------------------------------===//
+
+let isTwoAddress = 1 in {
+ // MMXI_binop_rm - Simple MMX binary operator.
+ multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
+ ValueType OpVT, bit Commutable = 0> {
+ def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
+ [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
+ let isCommutable = Commutable;
+ }
+ def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
+ [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
+ (bitconvert
+ (loadv2i32 addr:$src2)))))]>;
+ }
+}
+
+let isTwoAddress = 1 in {
+ multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
+ bit Commutable = 0> {
+ def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
+ [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
+ let isCommutable = Commutable;
+ }
+ def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
+ [(set VR64:$dst, (IntId VR64:$src1,
+ (bitconvert (loadv2i32 addr:$src2))))]>;
+ }
+}
+
+//===----------------------------------------------------------------------===//
// MMX EMMS Instruction
//===----------------------------------------------------------------------===//
@@ -54,6 +90,17 @@
// MMX Scalar Instructions
//===----------------------------------------------------------------------===//
+// Arithmetic Instructions
+defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
+defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
+defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
+
+defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
+defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
+
+defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
+defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
+
// Move Instructions
def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
"movd {$src, $dst|$dst, $src}", []>;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.206 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.207
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.206 Tue Feb 27 18:20:26 2007
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Thu Mar 8 16:09:11 2007
@@ -89,6 +89,8 @@
Opc = X86::MOVSDmr;
} else if (RC == &X86::VR128RegClass) {
Opc = X86::MOVAPSmr;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MOVQ64mr;
} else {
assert(0 && "Unknown regclass");
abort();
@@ -122,6 +124,8 @@
Opc = X86::MOVSDrm;
} else if (RC == &X86::VR128RegClass) {
Opc = X86::MOVAPSrm;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MOVQ64rm;
} else {
assert(0 && "Unknown regclass");
abort();
@@ -154,6 +158,8 @@
Opc = X86::FsMOVAPDrr;
} else if (RC == &X86::VR128RegClass) {
Opc = X86::MOVAPSrr;
+ } else if (RC == &X86::VR64RegClass) {
+ Opc = X86::MOVQ64rr;
} else {
assert(0 && "Unknown regclass");
abort();
More information about the llvm-commits
mailing list