[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.250 -> 1.251
---
Log message:

Fix ixaddrs as well, allowing ppc64 to compile to:

_test2:
        li r2, 0
        lis r3, 1
        std r2, 9024(r3)
        blr 

instead of:

_test2:
        lis r2, 1
        li r3, 0
        ori r2, r2, 9024
        std r3, 0(r2)
        blr 

This implements CodeGen/PowerPC/LargeAbsoluteAddr.ll:test2



---
Diffs of the changes:  (+24 -19)

 PPCISelLowering.cpp |   43 ++++++++++++++++++++++++-------------------
 1 files changed, 24 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.250 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.251
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.250	Sat Feb 17 00:44:03 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sat Feb 17 00:57:26 2007
@@ -841,25 +841,30 @@
       }
     }
   } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
-    // Loading from a constant address.
-    
-    // If this address fits entirely in a 14-bit sext immediate field, codegen
-    // this as "d, 0"
-    short Imm;
-    if (isIntS16Immediate(CN, Imm)) {
-      Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
-      Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
-      return true;
-    }
-    
-    // FIXME: Handle small sext constant offsets in PPC64 mode also!
-    if (CN->getValueType(0) == MVT::i32) {
-      int Addr = (int)CN->getValue();
-      
-      // Otherwise, break this down into an LIS + disp.
-      Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
-      Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
-      return true;
+    // Loading from a constant address.  Verify low two bits are clear.
+    if ((CN->getValue() & 3) == 0) {
+      // If this address fits entirely in a 14-bit sext immediate field, codegen
+      // this as "d, 0"
+      short Imm;
+      if (isIntS16Immediate(CN, Imm)) {
+        Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
+        Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
+        return true;
+      }
+    
+      // Fold the low-part of 32-bit absolute addresses into addr mode.
+      if (CN->getValueType(0) == MVT::i32 ||
+          (int64_t)CN->getValue() == (int)CN->getValue()) {
+        int Addr = (int)CN->getValue();
+      
+        // Otherwise, break this down into an LIS + disp.
+        Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
+        
+        Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
+        unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
+        Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
+        return true;
+      }
     }
   }