[llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)

[Evan Cheng]

Hi Lauro,

Thanks for taking a crack at this! Your work is much appreciated.

However, I have some comments. :-)

1. I think rather than adding a constraint that says a source operand  
must not be assigned the same register as another. It would be better  
if you add a constraint that says a source operand "can be killed at  
issue cycle + n". The live range analysis current assumes every  
source operand read is completed at issue cycle + 0 and write back  
happens at issue cycle + 2. By changing the read latency to 2 you can  
force a source operand to conflict with a destination operand.

2. Please write more comments. :-)

Thanks,

Evan

On Jan 25, 2007, at 1:54 PM, Lauro Ramos Venancio wrote:

> This patch implements the instruction constraint DestReg!=SrcReg. It
> is needed by ARM backend.
>
> A sample of use of this constraint is following:
>
> class RegConstraint<string C> {
>  string Constraints = C;
> }
>
> // AI_orr - Defines a (op r, r) pattern.
> class AI_orr<string opc, SDNode opnode>
>  : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
>       !strconcat(opc, " $dst, $a, $b"),
>       [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
>        RegConstraint<"$dst != $a">;
>
>
> Lauro
> <constraint.patch>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits