[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp IA64ISelLowering.h

[Reid Spencer]

Changes in directory llvm/lib/Target/IA64:

IA64ISelLowering.cpp updated: 1.50 -> 1.51
IA64ISelLowering.h updated: 1.7 -> 1.8
---
Log message:

For PR950: http://llvm.org/PR950 :
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
   type of an function parameter was used to determine whether it should
   be sign extended or zero extended before the call. This information is
   now communicated via the function type's parameter attributes. 
3. The interface to LowerCallTo had to be changed in order to accommodate
   the parameter attribute information. Although it would have been
   convenient to pass in the FunctionType itself, there isn't always one
   present in the caller. Consequently, a signedness indication for the
   result type and for each parameter was provided for in the interface
   to this method. All implementations were changed to make the adjustment
   necessary.


---
Diffs of the changes:  (+20 -19)

 IA64ISelLowering.cpp |   32 +++++++++++++++++---------------
 IA64ISelLowering.h   |    7 +++----
 2 files changed, 20 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.50 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.51
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.50	Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp	Sat Dec 30 23:55:36 2006
@@ -290,10 +290,10 @@
 
 std::pair<SDOperand, SDOperand>
 IA64TargetLowering::LowerCallTo(SDOperand Chain,
-                                const Type *RetTy, bool isVarArg,
-                                unsigned CallingConv, bool isTailCall,
-                                SDOperand Callee, ArgListTy &Args,
-                                SelectionDAG &DAG) {
+                                const Type *RetTy, bool RetTyIsSigned, 
+                                bool isVarArg, unsigned CallingConv, 
+                                bool isTailCall, SDOperand Callee, 
+                                ArgListTy &Args, SelectionDAG &DAG) {
 
   MachineFunction &MF = DAG.getMachineFunction();
 
@@ -315,7 +315,8 @@
     std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
 
   // keep stack frame 16-byte aligned
-  //assert(NumBytes==((NumBytes+15) & ~15) && "stack frame not 16-byte aligned!");
+  // assert(NumBytes==((NumBytes+15) & ~15) && 
+  //        "stack frame not 16-byte aligned!");
   NumBytes = (NumBytes+15) & ~15;
   
   Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
@@ -328,7 +329,7 @@
   
   for (unsigned i = 0, e = Args.size(); i != e; ++i)
     {
-      SDOperand Val = Args[i].first;
+      SDOperand Val = Args[i].Node;
       MVT::ValueType ObjectVT = Val.getValueType();
       SDOperand ValToStore(0, 0), ValToConvert(0, 0);
       unsigned ObjSize=8;
@@ -337,14 +338,15 @@
       case MVT::i1:
       case MVT::i8:
       case MVT::i16:
-      case MVT::i32:
+      case MVT::i32: {
         //promote to 64-bits, sign/zero extending based on type
         //of the argument
-        if(Args[i].second->isSigned())
-          Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Val);
-        else
-          Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Val);
+        ISD::NodeType ExtendKind = ISD::ZERO_EXTEND;
+        if (Args[i].isSigned)
+          ExtendKind = ISD::SIGN_EXTEND;
+        Val = DAG.getNode(ExtendKind, MVT::i64, Val);
         // XXX: fall through
+      }
       case MVT::i64:
         //ObjSize = 8;
         if(RegValuesToPass.size() >= 8) {
@@ -422,7 +424,8 @@
   unsigned seenConverts = 0;
   for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
     if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
-      Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], InFlag);
+      Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], 
+                               InFlag);
       InFlag = Chain.getValue(1);
     }
   }
@@ -432,8 +435,7 @@
   for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
     Chain = DAG.getCopyToReg(Chain,
       MVT::isInteger(RegValuesToPass[i].getValueType()) ?
-                                          IntArgRegs[i] : FPArgRegs[usedFPArgs++],
-      RegValuesToPass[i], InFlag);
+        IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
     InFlag = Chain.getValue(1);
   }
 
@@ -483,7 +485,7 @@
     case MVT::i1: { // bools are just like other integers (returned in r8)
       // we *could* fall through to the truncate below, but this saves a
       // few redundant predicate ops
-      SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
+      SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
       InFlag = boolInR8.getValue(2);
       Chain = boolInR8.getValue(1);
       SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);


Index: llvm/lib/Target/IA64/IA64ISelLowering.h
diff -u llvm/lib/Target/IA64/IA64ISelLowering.h:1.7 llvm/lib/Target/IA64/IA64ISelLowering.h:1.8
--- llvm/lib/Target/IA64/IA64ISelLowering.h:1.7	Fri Jan 27 15:09:22 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.h	Sat Dec 30 23:55:36 2006
@@ -58,10 +58,9 @@
     /// LowerCallTo - This hook lowers an abstract call to a function into an
     /// actual call.
     virtual std::pair<SDOperand, SDOperand>
-      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
-                  unsigned CC,
-                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
-                  SelectionDAG &DAG);
+      LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 
+                  bool isVarArg, unsigned CC, bool isTailCall, 
+                  SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
     
     /// LowerOperation - for custom lowering specific ops
     /// (currently, only "ret void")