[llvm-commits] CVS: llvm/lib/Target/X86/X86CodeEmitter.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.h X86InstrX86-64.td X86JITInfo.cpp X86Relocations.h
Evan Cheng
evan.cheng at apple.com
Mon Dec 4 20:01:18 PST 2006
Changes in directory llvm/lib/Target/X86:
X86CodeEmitter.cpp updated: 1.124 -> 1.125
X86ISelDAGToDAG.cpp updated: 1.133 -> 1.134
X86ISelLowering.cpp updated: 1.300 -> 1.301
X86InstrInfo.h updated: 1.60 -> 1.61
X86InstrX86-64.td updated: 1.9 -> 1.10
X86JITInfo.cpp updated: 1.32 -> 1.33
X86Relocations.h updated: 1.3 -> 1.4
---
Log message:
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
---
Diffs of the changes: (+126 -129)
X86CodeEmitter.cpp | 171 ++++++++++++++++++++++++++++++----------------------
X86ISelDAGToDAG.cpp | 18 ++---
X86ISelLowering.cpp | 39 +----------
X86InstrInfo.h | 4 -
X86InstrX86-64.td | 13 ---
X86JITInfo.cpp | 3
X86Relocations.h | 7 +-
7 files changed, 126 insertions(+), 129 deletions(-)
Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.124 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.125
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.124 Fri Dec 1 15:52:58 2006
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp Mon Dec 4 22:01:03 2006
@@ -59,12 +59,12 @@
void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
void emitPCRelativeValue(intptr_t Address);
void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
- void emitGlobalAddressForPtr(GlobalValue *GV, bool isPCRelative,
+ void emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
int Disp = 0, unsigned PCAdj = 0);
- void emitExternalSymbolAddress(const char *ES, bool isPCRelative);
- void emitPCRelativeConstPoolAddress(unsigned CPI, int Disp = 0,
- unsigned PCAdj = 0);
- void emitPCRelativeJumpTableAddress(unsigned JTI, unsigned PCAdj = 0);
+ void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
+ void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
+ unsigned PCAdj = 0);
+ void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0);
void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
unsigned PCAdj = 0);
@@ -144,41 +144,45 @@
/// emitGlobalAddress - Emit the specified address to the code stream assuming
/// this is part of a "take the address of a global" instruction.
///
-void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, bool isPCRelative,
+void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
int Disp /* = 0 */,
unsigned PCAdj /* = 0 */) {
- unsigned rt = isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), rt,
+ MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
GV, PCAdj));
+ if (Reloc == X86::reloc_absolute_dword)
+ MCE.emitWordLE(0);
MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
}
/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative) {
+void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
- isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
+ Reloc, ES));
+ if (Reloc == X86::reloc_absolute_dword)
+ MCE.emitWordLE(0);
MCE.emitWordLE(0);
}
-/// emitPCRelativeConstPoolAddress - Arrange for the address of an constant pool
+/// emitConstPoolAddress - Arrange for the address of an constant pool
/// to be emitted to the current location in the function, and allow it to be PC
/// relative.
-void Emitter::emitPCRelativeConstPoolAddress(unsigned CPI, int Disp /* = 0 */,
- unsigned PCAdj /* = 0 */) {
+void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
+ int Disp /* = 0 */,
+ unsigned PCAdj /* = 0 */) {
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
- X86::reloc_pcrel_word, CPI, PCAdj));
+ Reloc, CPI, PCAdj));
MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
}
-/// emitPCRelativeJumpTableAddress - Arrange for the address of a jump table to
+/// emitJumpTableAddress - Arrange for the address of a jump table to
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
-void Emitter::emitPCRelativeJumpTableAddress(unsigned JTI,
- unsigned PCAdj /* = 0 */) {
+void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
+ unsigned PCAdj /* = 0 */) {
MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
- X86::reloc_pcrel_word, JTI, PCAdj));
+ Reloc, JTI, PCAdj));
MCE.emitWordLE(0); // The relocated value will be added to the displacement
}
@@ -291,15 +295,17 @@
// But it's probably not beneficial.
// 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
// 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
- emitGlobalAddressForPtr(RelocOp->getGlobal(), Is64BitMode,
+ unsigned rt= Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
+ emitGlobalAddressForPtr(RelocOp->getGlobal(), rt,
RelocOp->getOffset(), PCAdj);
} else if (RelocOp->isConstantPoolIndex()) {
// Must be in 64-bit mode.
- emitPCRelativeConstPoolAddress(RelocOp->getConstantPoolIndex(),
- RelocOp->getOffset(), PCAdj);
+ emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word,
+ RelocOp->getOffset(), PCAdj);
} else if (RelocOp->isJumpTableIndex()) {
// Must be in 64-bit mode.
- emitPCRelativeJumpTableAddress(RelocOp->getJumpTableIndex(), PCAdj);
+ emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word,
+ PCAdj);
} else {
assert(0 && "Unknown value to relocate!");
}
@@ -417,8 +423,8 @@
}
}
-static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
- switch (Desc.TSFlags & X86II::ImmMask) {
+static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
+ switch (Desc->TSFlags & X86II::ImmMask) {
case X86II::Imm8: return 1;
case X86II::Imm16: return 2;
case X86II::Imm32: return 4;
@@ -459,19 +465,19 @@
/// size, and 3) use of X86-64 extended registers.
unsigned Emitter::determineREX(const MachineInstr &MI) {
unsigned REX = 0;
- unsigned Opcode = MI.getOpcode();
- const TargetInstrDescriptor &Desc = II->get(Opcode);
+ const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
+ unsigned Opcode = Desc->Opcode;
// Pseudo instructions do not need REX prefix byte.
- if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
+ if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
return 0;
- if (Desc.TSFlags & X86II::REX_W)
+ if (Desc->TSFlags & X86II::REX_W)
REX |= 1 << 3;
- unsigned NumOps = II->getNumOperands(Opcode);
+ unsigned NumOps = Desc->numOperands;
if (NumOps) {
bool isTwoAddr = NumOps > 1 &&
- II->getOperandConstraint(Opcode, 1, TOI::TIED_TO) != -1;
+ Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
bool isTrunc8 = isX86_64TruncToByte(Opcode);
@@ -489,7 +495,7 @@
}
}
- switch (Desc.TSFlags & X86II::FormMask) {
+ switch (Desc->TSFlags & X86II::FormMask) {
case X86II::MRMInitReg:
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= (1 << 0) | (1 << 2);
@@ -559,20 +565,20 @@
void Emitter::emitInstruction(const MachineInstr &MI) {
NumEmitted++; // Keep track of the # of mi's emitted
- unsigned Opcode = MI.getOpcode();
- const TargetInstrDescriptor &Desc = II->get(Opcode);
+ const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
+ unsigned Opcode = Desc->Opcode;
// Emit the repeat opcode prefix as needed.
- if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
+ if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
// Emit the operand size opcode prefix as needed.
- if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
+ if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
// Emit the address size opcode prefix as needed.
- if (Desc.TSFlags & X86II::AdSize) MCE.emitByte(0x67);
+ if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
bool Need0FPrefix = false;
- switch (Desc.TSFlags & X86II::Op0Mask) {
+ switch (Desc->TSFlags & X86II::Op0Mask) {
case X86II::TB:
Need0FPrefix = true; // Two-byte opcode prefix
break;
@@ -588,7 +594,7 @@
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
MCE.emitByte(0xD8+
- (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
+ (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
>> X86II::Op0Shift));
break; // Two-byte opcode prefix
default: assert(0 && "Invalid prefix!");
@@ -607,14 +613,13 @@
MCE.emitByte(0x0F);
// If this is a two-address instruction, skip one of the register operands.
- unsigned NumOps = II->getNumOperands(Opcode);
+ unsigned NumOps = Desc->numOperands;
unsigned CurOp = 0;
- if (NumOps > 1 &&
- II->getOperandConstraint(Opcode, 1, TOI::TIED_TO) != -1)
+ if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
CurOp++;
- unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
- switch (Desc.TSFlags & X86II::FormMask) {
+ unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
+ switch (Desc->TSFlags & X86II::FormMask) {
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
#ifndef NDEBUG
@@ -651,7 +656,7 @@
Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
emitGlobalAddressForCall(MO.getGlobal(), !isTailCall);
} else if (MO.isExternalSymbol()) {
- emitExternalSymbolAddress(MO.getSymbolName(), true);
+ emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
} else if (MO.isImmediate()) {
emitConstant(MO.getImm(), sizeOfImm(Desc));
} else {
@@ -665,20 +670,22 @@
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
- if (MO1.isGlobalAddress()) {
- assert(sizeOfImm(Desc) == TD->getPointerSize() &&
- "Don't know how to emit non-pointer values!");
- emitGlobalAddressForPtr(MO1.getGlobal(), Is64BitMode, MO1.getOffset());
- } else if (MO1.isExternalSymbol()) {
- assert(sizeOfImm(Desc) == TD->getPointerSize() &&
- "Don't know how to emit non-pointer values!");
- emitExternalSymbolAddress(MO1.getSymbolName(), false);
- } else if (MO1.isJumpTableIndex()) {
- assert(sizeOfImm(Desc) == TD->getPointerSize() &&
- "Don't know how to emit non-pointer values!");
- emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
- } else {
- emitConstant(MO1.getImm(), sizeOfImm(Desc));
+ unsigned Size = sizeOfImm(Desc);
+ if (MO1.isImmediate())
+ emitConstant(MO1.getImm(), Size);
+ else {
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
+ // FIXME
+ if (Opcode == X86::MOV64ri)
+ rt = X86::reloc_absolute_dword;
+ if (MO1.isGlobalAddress())
+ emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
+ else if (MO1.isExternalSymbol())
+ emitExternalSymbolAddress(MO1.getSymbolName(), rt);
+ else if (MO1.isConstantPoolIndex())
+ emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
+ else if (MO1.isJumpTableIndex())
+ emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
}
}
break;
@@ -728,10 +735,28 @@
case X86II::MRM6r: case X86II::MRM7r:
MCE.emitByte(BaseOpcode);
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
- (Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
+ (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
- if (CurOp != NumOps && MI.getOperand(CurOp).isImmediate())
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ if (CurOp != NumOps) {
+ const MachineOperand &MO1 = MI.getOperand(CurOp++);
+ unsigned Size = sizeOfImm(Desc);
+ if (MO1.isImmediate())
+ emitConstant(MO1.getImm(), Size);
+ else {
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
+ // FIXME
+ if (Opcode == X86::MOV64ri32)
+ rt = X86::reloc_absolute_word;
+ if (MO1.isGlobalAddress())
+ emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
+ else if (MO1.isExternalSymbol())
+ emitExternalSymbolAddress(MO1.getSymbolName(), rt);
+ else if (MO1.isConstantPoolIndex())
+ emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
+ else if (MO1.isJumpTableIndex())
+ emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
+ }
+ }
break;
case X86II::MRM0m: case X86II::MRM1m:
@@ -742,20 +767,26 @@
(MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
MCE.emitByte(BaseOpcode);
- emitMemModRMByte(MI, CurOp, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m,
+ emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
PCAdj);
CurOp += 4;
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
+ unsigned Size = sizeOfImm(Desc);
if (MO.isImmediate())
- emitConstant(MO.getImm(), sizeOfImm(Desc));
- else if (MO.isGlobalAddress())
- emitGlobalAddressForPtr(MO.getGlobal(), Is64BitMode, MO.getOffset());
- else if (MO.isJumpTableIndex())
- emitConstant(MCE.getJumpTableEntryAddress(MO.getJumpTableIndex()), 4);
- else
- assert(0 && "Unknown operand!");
+ emitConstant(MO.getImm(), Size);
+ else {
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
+ if (MO.isGlobalAddress())
+ emitGlobalAddressForPtr(MO.getGlobal(), rt, MO.getOffset());
+ else if (MO.isExternalSymbol())
+ emitExternalSymbolAddress(MO.getSymbolName(), rt);
+ else if (MO.isConstantPoolIndex())
+ emitConstPoolAddress(MO.getConstantPoolIndex(), rt);
+ else if (MO.isJumpTableIndex())
+ emitJumpTableAddress(MO.getJumpTableIndex(), rt);
+ }
}
break;
}
@@ -769,6 +800,6 @@
break;
}
- assert((Desc.Flags & M_VARIABLE_OPS) != 0 ||
+ assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
CurOp == NumOps && "Unknown encoding!");
}
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.133 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.134
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.133 Thu Nov 30 15:55:46 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Dec 4 22:01:03 2006
@@ -590,11 +590,10 @@
break;
}
- case X86ISD::Wrapper:
- case X86ISD::WrapperRIP: {
- bool isRIP = N.getOpcode() == X86ISD::WrapperRIP;
+ case X86ISD::Wrapper: {
+ bool is64Bit = Subtarget->is64Bit();
// Under X86-64 non-small code model, GV (and friends) are 64-bits.
- if (!isRIP && Subtarget->is64Bit() && TM.getCodeModel() != CodeModel::Small)
+ if (is64Bit && TM.getCodeModel() != CodeModel::Small)
break;
// If value is available in a register both base and index components have
@@ -603,7 +602,7 @@
if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
// For X86-64 PIC code, only allow GV / CP + displacement so we can use
// RIP relative addressing mode.
- if (isRIP &&
+ if (is64Bit &&
(AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
AM.BaseType == X86ISelAddressMode::FrameIndexBase))
break;
@@ -613,7 +612,7 @@
AM.CP = CP->getConstVal();
AM.Align = CP->getAlignment();
AM.Disp += CP->getOffset();
- AM.isRIPRel = isRIP;
+ AM.isRIPRel = is64Bit;
return false;
}
} else if (GlobalAddressSDNode *G =
@@ -621,10 +620,10 @@
if (AM.GV == 0) {
AM.GV = G->getGlobal();
AM.Disp += G->getOffset();
- AM.isRIPRel = isRIP;
+ AM.isRIPRel = is64Bit;
return false;
}
- } else if (isRoot && isRIP) {
+ } else if (isRoot && is64Bit) {
if (ExternalSymbolSDNode *S =
dyn_cast<ExternalSymbolSDNode>(N.getOperand(0))) {
AM.ES = S->getSymbol();
@@ -997,8 +996,7 @@
SDOperand N0 = N.getOperand(0);
SDOperand N1 = N.getOperand(1);
if (N.Val->getValueType(0) == PtrVT &&
- (N0.getOpcode() == X86ISD::Wrapper
- || N0.getOpcode() == X86ISD::WrapperRIP) &&
+ N0.getOpcode() == X86ISD::Wrapper &&
N1.getOpcode() == ISD::Constant) {
unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
SDOperand C(0, 0);
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.300 llvm/lib/Target/X86/X86ISelLowering.cpp:1.301
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.300 Mon Dec 4 16:38:21 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Dec 4 22:01:03 2006
@@ -3832,14 +3832,7 @@
SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
getPointerTy(),
CP->getAlignment());
- // Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
- TargetMachine &tm = getTargetMachine();
- unsigned WrapperOpcode = (Subtarget->is64Bit() &&
- (tm.getCodeModel() == CodeModel::Small ||
- tm.getCodeModel() == CodeModel::Medium) &&
- tm.getRelocationModel() == Reloc::PIC_)
- ? X86ISD::WrapperRIP : X86ISD::Wrapper;
- Result = DAG.getNode(WrapperOpcode, getPointerTy(), Result);
+ Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
if (Subtarget->isTargetDarwin()) {
// With PIC, the address is actually $g + Offset.
if (!Subtarget->is64Bit() &&
@@ -3855,14 +3848,7 @@
X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
- // Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
- TargetMachine &tm = getTargetMachine();
- unsigned WrapperOpcode = (Subtarget->is64Bit() &&
- (tm.getCodeModel() == CodeModel::Small ||
- tm.getCodeModel() == CodeModel::Medium) &&
- tm.getRelocationModel() == Reloc::PIC_)
- ? X86ISD::WrapperRIP : X86ISD::Wrapper;
- Result = DAG.getNode(WrapperOpcode, getPointerTy(), Result);
+ Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
if (Subtarget->isTargetDarwin()) {
// With PIC, the address is actually $g + Offset.
if (!Subtarget->is64Bit() &&
@@ -3889,14 +3875,7 @@
X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
- // Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
- TargetMachine &tm = getTargetMachine();
- unsigned WrapperOpcode = (Subtarget->is64Bit() &&
- (tm.getCodeModel() == CodeModel::Small ||
- tm.getCodeModel() == CodeModel::Medium) &&
- tm.getRelocationModel() == Reloc::PIC_)
- ? X86ISD::WrapperRIP : X86ISD::Wrapper;
- Result = DAG.getNode(WrapperOpcode, getPointerTy(), Result);
+ Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
if (Subtarget->isTargetDarwin()) {
// With PIC, the address is actually $g + Offset.
if (!Subtarget->is64Bit() &&
@@ -4264,14 +4243,7 @@
SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
- // Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
- TargetMachine &tm = getTargetMachine();
- unsigned WrapperOpcode = (Subtarget->is64Bit() &&
- (tm.getCodeModel() == CodeModel::Small ||
- tm.getCodeModel() == CodeModel::Medium) &&
- tm.getRelocationModel() == Reloc::PIC_)
- ? X86ISD::WrapperRIP : X86ISD::Wrapper;
- Result = DAG.getNode(WrapperOpcode, getPointerTy(), Result);
+ Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
if (Subtarget->isTargetDarwin()) {
// With PIC, the address is actually $g + Offset.
if (!Subtarget->is64Bit() &&
@@ -5005,7 +4977,6 @@
case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
case X86ISD::Wrapper: return "X86ISD::Wrapper";
- case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
case X86ISD::S2VEC: return "X86ISD::S2VEC";
case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
case X86ISD::PINSRW: return "X86ISD::PINSRW";
@@ -5249,7 +5220,7 @@
/// node is a GlobalAddress + an offset.
static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
unsigned Opc = N->getOpcode();
- if (Opc == X86ISD::Wrapper || Opc == X86ISD::WrapperRIP) {
+ if (Opc == X86ISD::Wrapper) {
if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
return true;
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.60 llvm/lib/Target/X86/X86InstrInfo.h:1.61
--- llvm/lib/Target/X86/X86InstrInfo.h:1.60 Fri Dec 1 15:52:58 2006
+++ llvm/lib/Target/X86/X86InstrInfo.h Mon Dec 4 22:01:03 2006
@@ -277,8 +277,8 @@
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified opcode number.
//
- unsigned char getBaseOpcodeFor(unsigned Opcode) const {
- return get(Opcode).TSFlags >> X86II::OpcodeShift;
+ unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
+ return TID->TSFlags >> X86II::OpcodeShift;
}
};
Index: llvm/lib/Target/X86/X86InstrX86-64.td
diff -u llvm/lib/Target/X86/X86InstrX86-64.td:1.9 llvm/lib/Target/X86/X86InstrX86-64.td:1.10
--- llvm/lib/Target/X86/X86InstrX86-64.td:1.9 Thu Nov 30 15:55:46 2006
+++ llvm/lib/Target/X86/X86InstrX86-64.td Mon Dec 4 22:01:03 2006
@@ -36,7 +36,7 @@
// Complex Pattern Definitions...
//
def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
- [add, mul, shl, or, frameindex, X86WrapperRIP],
+ [add, mul, shl, or, frameindex, X86Wrapper],
[]>;
//===----------------------------------------------------------------------===//
@@ -1023,15 +1023,6 @@
// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
- (MOV64ri32 tconstpool :$dst)>, Requires<[SmallCode]>;
-def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
- (MOV64ri32 tjumptable :$dst)>, Requires<[SmallCode]>;
-def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
- (MOV64ri32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
-def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
- (MOV64ri32 texternalsym:$dst)>, Requires<[SmallCode]>;
-
-def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
(MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
(MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
@@ -1040,10 +1031,12 @@
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
(MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
+/*
def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
(MOV64mi32 addr:$dst, tglobaladdr:$src)>, Requires<[SmallCode]>;
def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
(MOV64mi32 addr:$dst, texternalsym:$src)>, Requires<[SmallCode]>;
+*/
// Calls
// Direct PC relative function call for small code model. 32-bit displacement
Index: llvm/lib/Target/X86/X86JITInfo.cpp
diff -u llvm/lib/Target/X86/X86JITInfo.cpp:1.32 llvm/lib/Target/X86/X86JITInfo.cpp:1.33
--- llvm/lib/Target/X86/X86JITInfo.cpp:1.32 Fri Nov 17 01:52:03 2006
+++ llvm/lib/Target/X86/X86JITInfo.cpp Mon Dec 4 22:01:03 2006
@@ -323,6 +323,9 @@
// in memory.
*((unsigned*)RelocPos) += (unsigned)ResultPtr;
break;
+ case X86::reloc_absolute_dword:
+ *((intptr_t*)RelocPos) += ResultPtr;
+ break;
}
}
}
Index: llvm/lib/Target/X86/X86Relocations.h
diff -u llvm/lib/Target/X86/X86Relocations.h:1.3 llvm/lib/Target/X86/X86Relocations.h:1.4
--- llvm/lib/Target/X86/X86Relocations.h:1.3 Wed May 24 12:04:04 2006
+++ llvm/lib/Target/X86/X86Relocations.h Mon Dec 4 22:01:03 2006
@@ -23,9 +23,10 @@
// the value already in memory, after we adjust it for where the PC is.
reloc_pcrel_word = 0,
- // reloc_absolute_word - Absolute relocation, just add the relocated value
- // to the value already in memory.
- reloc_absolute_word = 1
+ // reloc_absolute_word, reloc_absolute_dword - Absolute relocation, just
+ // add the relocated value to the value already in memory.
+ reloc_absolute_word = 1,
+ reloc_absolute_dword = 2
};
}
}
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