[llvm-commits] CVS: llvm/lib/Target/Sparc/DelaySlotFiller.cpp FPMover.cpp SparcISelDAGToDAG.cpp SparcInstrInfo.cpp SparcRegisterInfo.cpp SparcRegisterInfo.h
Evan Cheng
evan.cheng at apple.com
Mon Nov 27 15:37:44 PST 2006
Changes in directory llvm/lib/Target/Sparc:
DelaySlotFiller.cpp updated: 1.10 -> 1.11
FPMover.cpp updated: 1.13 -> 1.14
SparcISelDAGToDAG.cpp updated: 1.114 -> 1.115
SparcInstrInfo.cpp updated: 1.16 -> 1.17
SparcRegisterInfo.cpp updated: 1.47 -> 1.48
SparcRegisterInfo.h updated: 1.14 -> 1.15
---
Log message:
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
---
Diffs of the changes: (+38 -29)
DelaySlotFiller.cpp | 2 -
FPMover.cpp | 4 ++-
SparcISelDAGToDAG.cpp | 5 ++--
SparcInstrInfo.cpp | 2 -
SparcRegisterInfo.cpp | 53 +++++++++++++++++++++++++++-----------------------
SparcRegisterInfo.h | 1
6 files changed, 38 insertions(+), 29 deletions(-)
Index: llvm/lib/Target/Sparc/DelaySlotFiller.cpp
diff -u llvm/lib/Target/Sparc/DelaySlotFiller.cpp:1.10 llvm/lib/Target/Sparc/DelaySlotFiller.cpp:1.11
--- llvm/lib/Target/Sparc/DelaySlotFiller.cpp:1.10 Sat Feb 4 23:50:24 2006
+++ llvm/lib/Target/Sparc/DelaySlotFiller.cpp Mon Nov 27 17:37:22 2006
@@ -64,7 +64,7 @@
if (TII->hasDelaySlot(I->getOpcode())) {
MachineBasicBlock::iterator J = I;
++J;
- BuildMI(MBB, J, SP::NOP, 0);
+ BuildMI(MBB, J, TII->get(SP::NOP));
++FilledSlots;
Changed = true;
}
Index: llvm/lib/Target/Sparc/FPMover.cpp
diff -u llvm/lib/Target/Sparc/FPMover.cpp:1.13 llvm/lib/Target/Sparc/FPMover.cpp:1.14
--- llvm/lib/Target/Sparc/FPMover.cpp:1.13 Thu May 4 12:52:23 2006
+++ llvm/lib/Target/Sparc/FPMover.cpp Mon Nov 27 17:37:22 2006
@@ -16,6 +16,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Debug.h"
#include <iostream>
@@ -109,7 +110,8 @@
DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
- MI = BuildMI(MBB, I, SP::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
+ MI = BuildMI(MBB, I, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
+ .addReg(OddSrcReg);
DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
}
++NumFpDs;
Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.114 llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.115
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.114 Wed Nov 8 14:33:40 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp Mon Nov 27 17:37:22 2006
@@ -873,6 +873,7 @@
MachineBasicBlock *
SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
+ const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
unsigned BROpcode;
unsigned CC;
// Figure out the conditional branch opcode to use for this select_cc.
@@ -908,7 +909,7 @@
MachineBasicBlock *thisMBB = BB;
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
- BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
+ BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
@@ -936,7 +937,7 @@
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
- BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
+ BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
Index: llvm/lib/Target/Sparc/SparcInstrInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.16 llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.17
--- llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.16 Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/Sparc/SparcInstrInfo.cpp Mon Nov 27 17:37:22 2006
@@ -102,5 +102,5 @@
const std::vector<MachineOperand> &Cond)const{
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
- BuildMI(&MBB, SP::BA, 1).addMBB(TBB);
+ BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
}
Index: llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.47 llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.48
--- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp:1.47 Wed Nov 15 14:58:11 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.cpp Mon Nov 27 17:37:22 2006
@@ -18,6 +18,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Type.h"
#include "llvm/ADT/STLExtras.h"
#include <iostream>
@@ -35,11 +36,14 @@
const TargetRegisterClass *RC) const {
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
+ BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg);
else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
+ BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg);
else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
+ BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
+ .addReg(SrcReg);
else
assert(0 && "Can't store this register to stack slot");
}
@@ -49,11 +53,11 @@
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
+ BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
else
assert(0 && "Can't load this register from stack slot");
}
@@ -63,12 +67,12 @@
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
if (RC == SP::IntRegsRegisterClass)
- BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
+ BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
else if (RC == SP::FPRegsRegisterClass)
- BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
else if (RC == SP::DFPRegsRegisterClass)
- BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
- 1, DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
+ .addReg(SrcReg);
else
assert (0 && "Can't copy this register");
}
@@ -83,10 +87,10 @@
if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
if (OpNum == 0) // COPY -> STORE
- NewMI = BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
+ NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
.addReg(MI->getOperand(2).getReg());
else // COPY -> LOAD
- NewMI = BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
+ NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
.addFrameIndex(FI).addImm(0);
}
break;
@@ -95,10 +99,10 @@
// FALLTHROUGH
case SP::FMOVD:
if (OpNum == 0) // COPY -> STORE
- NewMI = BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
+ NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
.addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
else // COPY -> LOAD
- NewMI = BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
+ NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
break;
}
@@ -128,7 +132,7 @@
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
if (Size)
- BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
+ BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
MBB.erase(I);
}
@@ -158,10 +162,10 @@
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time.
unsigned OffHi = (unsigned)Offset >> 10U;
- BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
+ BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
- BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
- SP::G1).addReg(SP::G1).addReg(SP::I6);
+ BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
+ .addReg(SP::I6);
// Insert: G1+%lo(offset) into the user.
MI.getOperand(i).ChangeToRegister(SP::G1, false);
MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
@@ -192,19 +196,19 @@
NumBytes = -NumBytes;
if (NumBytes >= -4096) {
- BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
+ BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
SP::O6).addImm(NumBytes).addReg(SP::O6);
} else {
MachineBasicBlock::iterator InsertPt = MBB.begin();
// Emit this the hard way. This clobbers G1 which we always know is
// available here.
unsigned OffHi = (unsigned)NumBytes >> 10U;
- BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
+ BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
- BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
+ BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
- BuildMI(MBB, InsertPt, SP::SAVErr, 2,
- SP::O6).addReg(SP::O6).addReg(SP::G1);
+ BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
+ .addReg(SP::O6).addReg(SP::G1);
}
}
@@ -213,7 +217,8 @@
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == SP::RETL &&
"Can only put epilog before 'retl' instruction!");
- BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
+ BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
+ .addReg(SP::G0);
}
unsigned SparcRegisterInfo::getRARegister() const {
Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h
diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.14 llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.15
--- llvm/lib/Target/Sparc/SparcRegisterInfo.h:1.14 Mon Nov 13 17:36:35 2006
+++ llvm/lib/Target/Sparc/SparcRegisterInfo.h Mon Nov 27 17:37:22 2006
@@ -20,6 +20,7 @@
namespace llvm {
class SparcSubtarget;
+class TargetInstrInfo;
class Type;
struct SparcRegisterInfo : public SparcGenRegisterInfo {
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