[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrFormats.td
Chris Lattner
sabre at nondot.org
Fri Nov 10 15:59:00 PST 2006
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.216 -> 1.217
PPCISelLowering.cpp updated: 1.222 -> 1.223
PPCInstr64Bit.td updated: 1.22 -> 1.23
PPCInstrFormats.td updated: 1.82 -> 1.83
---
Log message:
implement preinc support for r+i loads on ppc64
---
Diffs of the changes: (+71 -17)
PPCISelDAGToDAG.cpp | 31 +++++++++++++++++++++++--------
PPCISelLowering.cpp | 11 ++++++++++-
PPCInstr64Bit.td | 42 ++++++++++++++++++++++++++++++++++++++----
PPCInstrFormats.td | 4 ----
4 files changed, 71 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.216 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.217
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.216 Thu Nov 9 20:08:47 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Nov 10 17:58:44 2006
@@ -830,14 +830,29 @@
unsigned Opcode;
bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
- switch (LoadedVT) {
- default: assert(0 && "Invalid PPC load type!");
- case MVT::f64: Opcode = PPC::LFDU; break;
- case MVT::f32: Opcode = PPC::LFSU; break;
- case MVT::i32: Opcode = PPC::LWZU; break;
- case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
- case MVT::i8: Opcode = PPC::LBZU; break;
+ if (LD->getValueType(0) != MVT::i64) {
+ // Handle PPC32 integer and normal FP loads.
+ assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ switch (LoadedVT) {
+ default: assert(0 && "Invalid PPC load type!");
+ case MVT::f64: Opcode = PPC::LFDU; break;
+ case MVT::f32: Opcode = PPC::LFSU; break;
+ case MVT::i32: Opcode = PPC::LWZU; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU; break;
+ }
+ } else {
+ assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
+ assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ switch (LoadedVT) {
+ default: assert(0 && "Invalid PPC load type!");
+ case MVT::i64: Opcode = PPC::LDU; break;
+ case MVT::i32: Opcode = PPC::LWZU8; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU8; break;
+ }
}
SDOperand Offset = LD->getOffset();
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.222 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.223
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.222 Thu Nov 9 20:08:47 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 10 17:58:44 2006
@@ -53,9 +53,15 @@
// PowerPC does not have truncstore for i1.
setStoreXAction(MVT::i1, Promote);
- // PowerPC has i32 and i64 pre-inc load and store's.
+ // PowerPC has pre-inc load and store's.
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
+ setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
+ setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
@@ -870,6 +876,9 @@
SDOperand Ptr;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
+
+ // FIXME: PPC has no LWAU!
+
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ST = ST;
//Ptr = ST->getBasePtr();
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.22 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.23
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.22 Fri Oct 13 16:14:26 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td Fri Nov 10 17:58:45 2006
@@ -229,8 +229,8 @@
//
-let isLoad = 1, PPC970_Unit = 2 in {
// Sign extending loads.
+let isLoad = 1, PPC970_Unit = 2 in {
def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src),
"lha $rD, $src", LdStLHA,
[(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
@@ -248,7 +248,17 @@
[(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
PPC970_DGroup_Cracked;
+// Update forms.
+def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
+ ptr_rc:$rA),
+ "lhau $rD, $disp($rA)", LdStGeneral,
+ []>, RegConstraint<"$rA = $rA_result">;
+// NO LWAU!
+
+}
+
// Zero extending loads.
+let isLoad = 1, PPC970_Unit = 2 in {
def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src),
"lbz $rD, $src", LdStGeneral,
[(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
@@ -268,20 +278,44 @@
def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src),
"lwzx $rD, $src", LdStGeneral,
[(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
+
+
+// Update forms.
+def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
+ ptr_rc:$rA),
+ "lbzu $rD, $disp($rA)", LdStGeneral,
+ []>, RegConstraint<"$rA = $rA_result">;
+def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
+ ptr_rc:$rA),
+ "lhzu $rD, $disp($rA)", LdStGeneral,
+ []>, RegConstraint<"$rA = $rA_result">;
+def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
+ ptr_rc:$rA),
+ "lwzu $rD, $disp($rA)", LdStGeneral,
+ []>, RegConstraint<"$rA = $rA_result">;
+
+}
// Full 8-byte loads.
-def LD : DSForm_2<58, 0, (ops G8RC:$rD, memrix:$src),
+let isLoad = 1, PPC970_Unit = 2 in {
+def LD : DSForm_1<58, 0, (ops G8RC:$rD, memrix:$src),
"ld $rD, $src", LdStLD,
[(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
"ldx $rD, $src", LdStLD,
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
+
+def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$rA_result, i32imm:$disp,
+ ptr_rc:$rA),
+ "ldu $rD, $disp($rA)", LdStLD,
+ []>, RegConstraint<"$rA = $rA_result">, isPPC64;
+
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
// Normal stores.
-def STD : DSForm_2<62, 0, (ops G8RC:$rS, memrix:$dst),
+def STD : DSForm_1<62, 0, (ops G8RC:$rS, memrix:$dst),
"std $rS, $dst", LdStSTD,
[(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst),
@@ -293,7 +327,7 @@
[]>, isPPC64;
// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
-def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst),
+def STD_32 : DSForm_1<62, 0, (ops GPRC:$rT, memrix:$dst),
"std $rT, $dst", LdStSTD,
[(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.82 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.83
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.82 Fri Nov 10 11:51:02 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Fri Nov 10 17:58:45 2006
@@ -191,10 +191,6 @@
let Inst{30-31} = xo;
}
-class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr,
- InstrItinClass itin, list<dag> pattern>
- : DSForm_1<opcode, xo, OL, asmstr, itin, pattern>;
-
// 1.7.6 X-Form
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
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