[llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp

[Evan Cheng]

Changes in directory llvm/lib/CodeGen:

LiveIntervalAnalysis.cpp updated: 1.188 -> 1.189
---
Log message:

Proper check for two-addressness.

---
Diffs of the changes:  (+22 -7)

 LiveIntervalAnalysis.cpp |   29 ++++++++++++++++++++++-------
 1 files changed, 22 insertions(+), 7 deletions(-)


Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.188 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.189
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.188	Thu Nov  2 14:25:49 2006
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp	Thu Nov  2 21:04:46 2006
@@ -364,6 +364,25 @@
     std::cerr << "%reg" << reg;
 }
 
+/// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to
+/// two addr elimination.
+static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg,
+                                const TargetInstrInfo *TII) {
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO1 = MI->getOperand(i);
+    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
+      for (unsigned j = i+1; j < e; ++j) {
+        MachineOperand &MO2 = MI->getOperand(j);
+        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
+            TII->getOperandConstraint(MI->getOpcode(), j,
+                                      TargetInstrInfo::TIED_TO) == (int)i)
+          return true;
+      }
+    }
+  }
+  return false;
+}
+
 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
                                              MachineBasicBlock::iterator mi,
                                              unsigned MIIdx,
@@ -453,13 +472,9 @@
   } else {
     // If this is the second time we see a virtual register definition, it
     // must be due to phi elimination or two addr elimination.  If this is
-    // the result of two address elimination, then the vreg is the first
-    // operand, and is a def-and-use.
-    if (mi->getOperand(0).isRegister() &&
-        mi->getOperand(0).getReg() == interval.reg &&
-        mi->getNumOperands() > 1 && mi->getOperand(1).isRegister() && 
-        mi->getOperand(1).getReg() == interval.reg &&
-        mi->getOperand(0).isDef() && mi->getOperand(1).isUse()) {
+    // the result of two address elimination, then the vreg is one of the
+    // def-and-use register operand.
+    if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) {
       // If this is a two-address definition, then we have already processed
       // the live range.  The only problem is that we didn't realize there
       // are actually two values in the live interval.  Because of this we