[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp AlphaCodeEmitter.cpp AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp

[Reid Spencer]

Changes in directory llvm/lib/Target/Alpha:

AlphaAsmPrinter.cpp updated: 1.53 -> 1.54
AlphaCodeEmitter.cpp updated: 1.17 -> 1.18
AlphaISelDAGToDAG.cpp updated: 1.61 -> 1.62
AlphaISelLowering.cpp updated: 1.72 -> 1.73
---
Log message:

For PR786: http://llvm.org/PR786 :
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining 
issues when they see them. All changes pass DejaGnu tests and Olden.


---
Diffs of the changes:  (+0 -12)

 AlphaAsmPrinter.cpp   |    1 -
 AlphaCodeEmitter.cpp  |    5 -----
 AlphaISelDAGToDAG.cpp |    1 -
 AlphaISelLowering.cpp |    5 -----
 4 files changed, 12 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.53 llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.54
--- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.53	Tue Oct 24 15:32:14 2006
+++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp	Thu Nov  2 14:25:49 2006
@@ -97,7 +97,6 @@
 
 void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
   const MRegisterInfo &RI = *TM.getRegisterInfo();
-  int new_symbol;
 
   switch (MO.getType()) {
   case MachineOperand::MO_Register:


Index: llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
diff -u llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.17 llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.18
--- llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:1.17	Thu Jul 27 13:20:17 2006
+++ llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp	Thu Nov  2 14:25:49 2006
@@ -92,7 +92,6 @@
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
        I != E; ++I) {
     MachineInstr &MI = *I;
-    unsigned Opcode = MI.getOpcode();
     switch(MI.getOpcode()) {
     default:
       MCE.emitWordLE(getBinaryCodeForInstr(*I));
@@ -160,10 +159,6 @@
   } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
              || MO.isConstantPoolIndex()) {
     DEBUG(std::cerr << MO << " is a relocated op for " << MI << "\n";);
-    bool isExternal = MO.isExternalSymbol() ||
-      (MO.isGlobalAddress() &&
-       ( MO.getGlobal()->hasWeakLinkage() ||
-         MO.getGlobal()->isExternal()) );
     unsigned Reloc = 0;
     int Offset = 0;
     bool useGOT = false;


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.61 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.62
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.61	Tue Oct 31 17:46:56 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Thu Nov  2 14:25:49 2006
@@ -324,7 +324,6 @@
       //	val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
       break; //(zext (LDAH (LDA)))
     //Else use the constant pool
-    MachineConstantPool *CP = BB->getParent()->getConstantPool();
     ConstantInt *C = ConstantInt::get(Type::ULongTy, uval);
     SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
     SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.72 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.73
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.72	Wed Nov  1 21:05:26 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Thu Nov  2 14:25:49 2006
@@ -175,8 +175,6 @@
   SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
   SDOperand Zero = DAG.getConstant(0, PtrVT);
   
-  const TargetMachine &TM = DAG.getTarget();
-
   SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi,  MVT::i64, JTI,
 			     DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
   SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
@@ -207,7 +205,6 @@
 				       int &VarArgsOffset) {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
-  SSARegMap *RegMap = MF.getSSARegMap();
   std::vector<SDOperand> ArgValues;
   SDOperand Root = Op.getOperand(0);
 
@@ -225,7 +222,6 @@
     SDOperand ArgVal;
 
     if (ArgNo  < 6) {
-      unsigned Vreg;
       switch (ObjectVT) {
       default:
         std::cerr << "Unknown Type " << ObjectVT << "\n";
@@ -480,7 +476,6 @@
     //Expand only on constant case
     if (Op.getOperand(1).getOpcode() == ISD::Constant) {
       MVT::ValueType VT = Op.Val->getValueType(0);
-      unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
       SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
 	BuildUDIV(Op.Val, DAG, NULL) :
 	BuildSDIV(Op.Val, DAG, NULL);