[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.312 -> 1.313
---
Log message:

Allow the getRegForInlineAsmConstraint method to return a register class with
no fixes physreg.  Treat this as permission to use any register in the register
class.  When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time.  This eliminates a ton
of copies around common inline asms.  For example:

int test2(int Y, int X) {
  asm("foo %0, %1" : "=r"(X): "r"(X));
  return X;
}

now compiles to:

_test2:
        foo r3, r4
        blr

instead of:

_test2:
        mr r2, r4
        foo r2, r2
        mr r3, r2
        blr

GCC produces:

_test2:
        foo r4, r4
        mr r3,r4
        blr



---
Diffs of the changes:  (+32 -4)

 SelectionDAGISel.cpp |   36 ++++++++++++++++++++++++++++++++----
 1 files changed, 32 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.312 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.313
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.312	Tue Oct 31 17:06:00 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Wed Nov  1 19:41:49 2006
@@ -2231,6 +2231,8 @@
   MVT::ValueType RegVT;
   MVT::ValueType ValueVT = VT;
   
+  // If this is a constraint for a specific physical register, like {r17},
+  // assign it now.
   if (PhysReg.first) {
     if (VT == MVT::Other)
       ValueVT = *PhysReg.second->vt_begin();
@@ -2260,10 +2262,36 @@
     return RegsForValue(Regs, RegVT, ValueVT);
   }
   
-  // This is a reference to a register class.  Allocate NumRegs consecutive,
-  // available, registers from the class.
-  std::vector<unsigned> RegClassRegs =
-    TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
+  // Otherwise, if this was a reference to an LLVM register class, create vregs
+  // for this reference.
+  std::vector<unsigned> RegClassRegs;
+  if (PhysReg.second) {
+    // If this is an early clobber or tied register, our regalloc doesn't know
+    // how to maintain the constraint.  If it isn't, go ahead and create vreg
+    // and let the regalloc do the right thing.
+    if (!isOutReg || !isInReg) {
+      if (VT == MVT::Other)
+        ValueVT = *PhysReg.second->vt_begin();
+      RegVT = *PhysReg.second->vt_begin();
+
+      // Create the appropriate number of virtual registers.
+      SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
+      for (; NumRegs; --NumRegs)
+        Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
+      
+      return RegsForValue(Regs, RegVT, ValueVT);
+    }
+    
+    // Otherwise, we can't allocate it.  Let the code below figure out how to
+    // maintain these constraints.
+    RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
+    
+  } else {
+    // This is a reference to a register class that doesn't directly correspond
+    // to an LLVM register class.  Allocate NumRegs consecutive, available,
+    // registers from the class.
+    RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
+  }
 
   const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
   MachineFunction &MF = *CurMBB->getParent();