[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.56 -> 1.57
ARMInstrInfo.td updated: 1.32 -> 1.33
---
Log message:

add optional input flag to FMRRD


---
Diffs of the changes:  (+4 -3)

 ARMISelDAGToDAG.cpp |    4 ++--
 ARMInstrInfo.td     |    3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.56 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.57
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.56	Fri Oct  6 14:10:05 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Fri Oct  6 15:33:26 2006
@@ -284,8 +284,8 @@
 
       Ops.push_back(DAG.getRegister(Reg2, MVT::i32));
       SDVTList    VTs = DAG.getVTList(MVT::Other, MVT::Flag);
-      SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg}; //missing flag
-      Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
+      SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg, InFlag};
+      Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, InFlag.Val ? 5 : 4);
     } else {
       if (VT == MVT::f32)
         Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg);


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.32 llvm/lib/Target/ARM/ARMInstrInfo.td:1.33
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.32	Thu Oct  5 11:48:49 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Fri Oct  6 15:33:26 2006
@@ -78,7 +78,8 @@
 def armfsitod      : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
 
 def SDTarmfmrrd    : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
-def armfmrrd       : SDNode<"ARMISD::FMRRD", SDTarmfmrrd, [SDNPHasChain, SDNPOutFlag]>;
+def armfmrrd       : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
+                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
 def SDTarmfmdrr    : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
 def armfmdrr       : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;