[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Chris Lattner sabre at nondot.org
Fri Oct 6 10:34:27 PDT 2006



Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.403 -> 1.404
---
Log message:

Fix a miscompilation of:

long long foo(long long X) {
  return (long long)(signed char)(int)X;
}

Instead of:

_foo:
        extsb r2, r4
        srawi r3, r4, 31
        mr r4, r2
        blr

we now produce:

_foo:
        extsb r4, r4
        srawi r3, r4, 31
        blr

This fixes a miscompilation in ConstantFolding.cpp.



---
Diffs of the changes:  (+5 -3)

 LegalizeDAG.cpp |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.403 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.404
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.403	Thu Oct  5 17:57:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Oct  6 12:34:12 2006
@@ -4349,12 +4349,14 @@
     
   case ISD::SIGN_EXTEND_INREG:
     ExpandOp(Node->getOperand(0), Lo, Hi);
-    // Sign extend the lo-part.
+    // sext_inreg the low part if needed.
+    Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
+    
+    // The high part gets the sign extension from the lo-part.  This handles
+    // things like sextinreg V:i64 from i8.
     Hi = DAG.getNode(ISD::SRA, NVT, Lo,
                      DAG.getConstant(MVT::getSizeInBits(NVT)-1,
                                      TLI.getShiftAmountTy()));
-    // sext_inreg the low part if needed.
-    Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
     break;
 
   case ISD::BSWAP: {






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