[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelDAGToDAG.cpp updated: 1.106 -> 1.107
---
Log message:

Fix a regression in the 32-bit port from the 64-bit port landing.
We now compile CodeGen/X86/lea-2.ll into:

_test:
        movl 4(%esp), %eax
        movl 8(%esp), %ecx
        leal -5(%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl 4(%esp), %eax
        leal (,%eax,4), %eax
        addl 8(%esp), %eax
        addl $4294967291, %eax
        ret



---
Diffs of the changes:  (+2 -2)

 X86ISelDAGToDAG.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.106 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.107
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.106	Tue Sep 12 16:03:39 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp	Tue Sep 12 23:45:25 2006
@@ -498,7 +498,7 @@
   // RIP relative addressing: %rip + 32-bit displacement!
   if (AM.isRIPRel) {
     if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
-      uint64_t Val = cast<ConstantSDNode>(N)->getValue();
+      int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
       if (isInt32(AM.Disp + Val)) {
         AM.Disp += Val;
         return false;
@@ -513,7 +513,7 @@
   switch (N.getOpcode()) {
   default: break;
   case ISD::Constant: {
-    uint64_t Val = cast<ConstantSDNode>(N)->getValue();
+    int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
     if (isInt32(AM.Disp + Val)) {
       AM.Disp += Val;
       return false;