[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMInstrInfo.td

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMAsmPrinter.cpp updated: 1.9 -> 1.10
ARMInstrInfo.td updated: 1.10 -> 1.11
---
Log message:

start comments with #
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save



---
Diffs of the changes:  (+21 -7)

 ARMAsmPrinter.cpp |   22 +++++++++++++++++-----
 ARMInstrInfo.td   |    6 ++++--
 2 files changed, 21 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.9 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.10
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.9	Tue Aug  1 07:58:43 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Tue Aug  1 13:53:10 2006
@@ -43,8 +43,8 @@
       Data32bitsDirective = "\t.word\t";
       Data64bitsDirective = 0;
       ZeroDirective = "\t.skip\t";
-      CommentString = "!";
-      ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
+      CommentString = "#";
+      ConstantPoolSection = "\t.text\n";
       AlignmentIsInBytes = false;
     }
 
@@ -60,9 +60,21 @@
     }
 
     void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
-      printOperand(MI, OpNo + 1);
-      O << ", ";
-      printOperand(MI, OpNo);
+      const MachineOperand &MO1 = MI->getOperand(OpNo);
+      const MachineOperand &MO2 = MI->getOperand(OpNo + 1);
+      assert(MO1.isImmediate());
+
+      if (MO2.isConstantPoolIndex()) {
+	printOperand(MI, OpNo + 1);
+      } else if (MO2.isRegister()) {
+	O << '[';
+	printOperand(MI, OpNo + 1);
+	O << ", ";
+	printOperand(MI, OpNo);
+	O << ']';
+      } else {
+	assert(0 && "Invalid Operand Type");
+      }
     }
 
     void printOperand(const MachineInstr *MI, int opNum);


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.10 llvm/lib/Target/ARM/ARMInstrInfo.td:1.11
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.10	Fri Jul 21 07:26:16 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue Aug  1 13:53:10 2006
@@ -57,10 +57,12 @@
   def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
 }
 
-def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+let  Defs = [R0, R1, R2, R3] in {
+  def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
+}
 
 def ldr   : InstARM<(ops IntRegs:$dst, memri:$addr),
-                     "ldr $dst, [$addr]",
+                     "ldr $dst, $addr",
                      [(set IntRegs:$dst, (load iaddr:$addr))]>;
 
 def str  : InstARM<(ops IntRegs:$src, IntRegs:$addr),