[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp ScheduleDAGRRList.cpp ScheduleDAGSimple.cpp SelectionDAGISel.cpp
Jim Laskey
jlaskey at apple.com
Tue Aug 1 11:30:08 PDT 2006
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGList.cpp updated: 1.63 -> 1.64
ScheduleDAGRRList.cpp updated: 1.10 -> 1.11
ScheduleDAGSimple.cpp updated: 1.14 -> 1.15
SelectionDAGISel.cpp updated: 1.263 -> 1.264
---
Log message:
1. Change use of "Cache" to "Default".
2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.
More to follow.
---
Diffs of the changes: (+23 -11)
ScheduleDAGList.cpp | 6 ++++--
ScheduleDAGRRList.cpp | 6 ++++--
ScheduleDAGSimple.cpp | 9 ++++++---
SelectionDAGISel.cpp | 13 +++++++++----
4 files changed, 23 insertions(+), 11 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.63 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.64
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.63 Tue Aug 1 09:21:23 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Aug 1 13:29:48 2006
@@ -21,6 +21,7 @@
#define DEBUG_TYPE "sched"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/ScheduleDAG.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetData.h"
@@ -519,9 +520,10 @@
/// createTDListDAGScheduler - This creates a top-down list scheduler with a
/// new hazard recognizer. This scheduler takes ownership of the hazard
/// recognizer and deletes it when done.
-ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG *DAG,
+ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGList(*DAG, BB, DAG->getTarget(),
new LatencyPriorityQueue(),
- new HazardRecognizer());
+ IS->CreateTargetHazardRecognizer());
}
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.10 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.11
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.10 Tue Aug 1 09:21:23 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Aug 1 13:29:48 2006
@@ -886,13 +886,15 @@
// Public Constructor Functions
//===----------------------------------------------------------------------===//
-llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
new BURegReductionPriorityQueue<bu_ls_rr_sort>());
}
-llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
new TDRegReductionPriorityQueue<td_ls_rr_sort>());
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.14 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.15
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.14 Tue Aug 1 09:21:23 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp Tue Aug 1 13:29:48 2006
@@ -1120,21 +1120,24 @@
/// createSimpleDAGScheduler - This creates a simple two pass instruction
/// scheduler using instruction itinerary.
-llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGSimple(false, false, *DAG, BB, DAG->getTarget());
}
/// createNoItinsDAGScheduler - This creates a simple two pass instruction
/// scheduler without using instruction itinerary.
-llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGSimple(false, true, *DAG, BB, DAG->getTarget());
}
/// createBFS_DAGScheduler - This creates a simple breadth first instruction
/// scheduler.
-llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG *DAG,
+llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB) {
return new ScheduleDAGSimple(true, false, *DAG, BB, DAG->getTarget());
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.263 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.264
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.263 Tue Aug 1 09:21:23 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Aug 1 13:29:48 2006
@@ -67,7 +67,7 @@
cl::init("default"),
cl::desc("Instruction schedulers available:"));
- RegisterScheduler
+ static RegisterScheduler
defaultListDAGScheduler("default", " Best scheduler for the target", NULL);
} // namespace
@@ -3611,7 +3611,7 @@
if (ViewSchedDAGs) DAG.viewGraph();
static RegisterScheduler::FunctionPassCtor Ctor =
- RegisterScheduler::getCache();
+ RegisterScheduler::getDefault();
if (!Ctor) {
if (std::string("default") == std::string(ISHeuristic)) {
@@ -3629,16 +3629,21 @@
Ctor = RegisterScheduler::FindCtor(ISHeuristic);
}
- RegisterScheduler::setCache(Ctor);
+ RegisterScheduler::setDefault(Ctor);
}
assert(Ctor && "No instruction scheduler found");
- ScheduleDAG *SL = Ctor(&DAG, BB);
+ ScheduleDAG *SL = Ctor(this, &DAG, BB);
BB = SL->Run();
delete SL;
}
+HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
+ return new HazardRecognizer();
+}
+
+
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
/// by tblgen. Others should not call it.
void SelectionDAGISel::
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