[llvm-commits] CVS: llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h MachinePassRegistry.h ScheduleDAG.h SelectionDAGISel.h
Jim Laskey
jlaskey at apple.com
Tue Aug 1 11:30:05 PDT 2006
Changes in directory llvm/include/llvm/CodeGen:
LinkAllCodegenComponents.h updated: 1.1 -> 1.2
MachinePassRegistry.h updated: 1.1 -> 1.2
ScheduleDAG.h updated: 1.28 -> 1.29
SelectionDAGISel.h updated: 1.21 -> 1.22
---
Log message:
1. Change use of "Cache" to "Default".
2. Added argument to instruction scheduler creators so the creators can do
special things.
3. Repaired target hazard code.
4. Misc.
More to follow.
---
Diffs of the changes: (+51 -31)
LinkAllCodegenComponents.h | 14 +++++++-------
MachinePassRegistry.h | 44 ++++++++++++++++++++++++++------------------
ScheduleDAG.h | 20 ++++++++++++++------
SelectionDAGISel.h | 4 ++++
4 files changed, 51 insertions(+), 31 deletions(-)
Index: llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h
diff -u llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.1 llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.2
--- llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h:1.1 Tue Aug 1 11:31:08 2006
+++ llvm/include/llvm/CodeGen/LinkAllCodegenComponents.h Tue Aug 1 13:29:48 2006
@@ -32,15 +32,15 @@
(void) llvm::createLocalRegisterAllocator();
(void) llvm::createLinearScanRegisterAllocator();
- (void) llvm::createBFS_DAGScheduler(NULL, NULL);
- (void) llvm::createSimpleDAGScheduler(NULL, NULL);
- (void) llvm::createNoItinsDAGScheduler(NULL, NULL);
- (void) llvm::createBURRListDAGScheduler(NULL, NULL);
- (void) llvm::createTDRRListDAGScheduler(NULL, NULL);
- (void) llvm::createTDListDAGScheduler(NULL, NULL);
+ (void) llvm::createBFS_DAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createSimpleDAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createNoItinsDAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL);
}
} ForceCodegenLinking; // Force link by creating a global definition.
}
-#endif
\ No newline at end of file
+#endif
Index: llvm/include/llvm/CodeGen/MachinePassRegistry.h
diff -u llvm/include/llvm/CodeGen/MachinePassRegistry.h:1.1 llvm/include/llvm/CodeGen/MachinePassRegistry.h:1.2
--- llvm/include/llvm/CodeGen/MachinePassRegistry.h:1.1 Tue Aug 1 11:31:08 2006
+++ llvm/include/llvm/CodeGen/MachinePassRegistry.h Tue Aug 1 13:29:48 2006
@@ -2,10 +2,18 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
+// This file was developed by the James M. Laskey and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file contains the mechanics for machine function pass registries. A
+// function pass registry (MachinePassRegistry) is auto filled by the static
+// constructors of MachinePassRegistryNode. Further there is a command line
+// parser (RegisterPassParser) which listens to each registry for additions
+// and deletions, so that the appropriate command option is updated.
+//
+//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_MACHINEPASSREGISTRY_H
#define LLVM_CODEGEN_MACHINEPASSREGISTRY_H
@@ -14,8 +22,6 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/CommandLine.h"
-#include <iostream>
-
namespace llvm {
@@ -83,7 +89,7 @@
MachinePassRegistryNode<FunctionPassCtor> *List;
// List of registry nodes.
- FunctionPassCtor Cache; // Cached function pass creator.
+ FunctionPassCtor Default; // Default function pass creator.
MachinePassRegistryListener* Listener;// Listener for list adds are removes.
public:
@@ -94,8 +100,8 @@
// Accessors.
//
MachinePassRegistryNode<FunctionPassCtor> *getList() { return List; }
- FunctionPassCtor getCache() { return Cache; }
- void setCache(FunctionPassCtor C) { Cache = C; }
+ FunctionPassCtor getDefault() { return Default; }
+ void setDefault(FunctionPassCtor C) { Default = C; }
void setListener(MachinePassRegistryListener *L) { Listener = L; }
/// Add - Adds a function pass to the registration list.
@@ -113,10 +119,8 @@
for (MachinePassRegistryNode<FunctionPassCtor> **I = &List;
*I; I = (*I)->getNextAddress()) {
if (*I == Node) {
-#if 0 // FIXME: Command opt needs to call a termination routine.
if (Listener) Listener->NotifyRemove(Node->getName(),
Node->getDescription());
-#endif
*I = (*I)->getNext();
break;
}
@@ -166,11 +170,11 @@
static RegisterRegAlloc *getList() {
return (RegisterRegAlloc *)Registry.getList();
}
- static FunctionPassCtor getCache() {
- return Registry.getCache();
+ static FunctionPassCtor getDefault() {
+ return Registry.getDefault();
}
- static void setCache(FunctionPassCtor C) {
- Registry.setCache(C);
+ static void setDefault(FunctionPassCtor C) {
+ Registry.setDefault(C);
}
static void setListener(MachinePassRegistryListener *L) {
Registry.setListener(L);
@@ -200,16 +204,19 @@
///
//===----------------------------------------------------------------------===//
+class SelectionDAGISel;
class ScheduleDAG;
class SelectionDAG;
class MachineBasicBlock;
class RegisterScheduler : public
- MachinePassRegistryNode<ScheduleDAG *(*)(SelectionDAG*, MachineBasicBlock*)> {
+ MachinePassRegistryNode<
+ ScheduleDAG *(*)(SelectionDAGISel*, SelectionDAG*, MachineBasicBlock*)> {
public:
- typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAG*, MachineBasicBlock*);
+ typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
+ MachineBasicBlock*);
static MachinePassRegistry<FunctionPassCtor> Registry;
@@ -228,11 +235,11 @@
static RegisterScheduler *getList() {
return (RegisterScheduler *)Registry.getList();
}
- static FunctionPassCtor getCache() {
- return Registry.getCache();
+ static FunctionPassCtor getDefault() {
+ return Registry.getDefault();
}
- static void setCache(FunctionPassCtor C) {
- Registry.setCache(C);
+ static void setDefault(FunctionPassCtor C) {
+ Registry.setDefault(C);
}
static void setListener(MachinePassRegistryListener *L) {
Registry.setListener(L);
@@ -267,6 +274,7 @@
public cl::parser<const char *> {
public:
RegisterPassParser() {}
+ ~RegisterPassParser() { RegistryClass::setListener(NULL); }
void initialize(cl::Option &O) {
cl::parser<const char *>::initialize(O);
Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.28 llvm/include/llvm/CodeGen/ScheduleDAG.h:1.29
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.28 Tue Aug 1 09:21:23 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h Tue Aug 1 13:29:48 2006
@@ -26,6 +26,7 @@
class MachineInstr;
class MRegisterInfo;
class SelectionDAG;
+ class SelectionDAGISel;
class SSARegMap;
class TargetInstrInfo;
class TargetInstrDescriptor;
@@ -223,31 +224,38 @@
/// createBFS_DAGScheduler - This creates a simple breadth first instruction
/// scheduler.
- ScheduleDAG *createBFS_DAGScheduler(SelectionDAG *DAG, MachineBasicBlock *BB);
+ ScheduleDAG *createBFS_DAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
+ MachineBasicBlock *BB);
/// createSimpleDAGScheduler - This creates a simple two pass instruction
/// scheduler using instruction itinerary.
- ScheduleDAG* createSimpleDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createSimpleDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createNoItinsDAGScheduler - This creates a simple two pass instruction
/// scheduler without using instruction itinerary.
- ScheduleDAG* createNoItinsDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createNoItinsDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
- ScheduleDAG* createBURRListDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
- ScheduleDAG* createTDRRListDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
- ScheduleDAG* createTDListDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
}
Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
diff -u llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.21 llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.22
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h:1.21 Tue Aug 1 09:21:23 2006
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.h Tue Aug 1 13:29:48 2006
@@ -67,6 +67,10 @@
/// folded during instruction selection?
virtual bool CanBeFoldedBy(SDNode *N, SDNode *U) { return true; }
+ /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
+ /// to use for this target when scheduling the DAG.
+ virtual HazardRecognizer *CreateTargetHazardRecognizer();
+
/// CaseBlock - This structure is used to communicate between SDLowering and
/// SDISel for the code generation of additional basic blocks needed by multi-
/// case switch statements.
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