[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrInfo.td ARMRegisterInfo.cpp
Rafael Espindola
rafael.espindola at gmail.com
Sun Jul 9 18:41:47 PDT 2006
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.13 -> 1.14
ARMInstrInfo.cpp updated: 1.3 -> 1.4
ARMInstrInfo.h updated: 1.1 -> 1.2
ARMInstrInfo.td updated: 1.5 -> 1.6
ARMRegisterInfo.cpp updated: 1.5 -> 1.6
---
Log message:
create the raddr addressing mode that matches any register and the frame index
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
---
Diffs of the changes: (+14 -51)
ARMISelDAGToDAG.cpp | 21 +++++++++------------
ARMInstrInfo.cpp | 22 ----------------------
ARMInstrInfo.h | 14 --------------
ARMInstrInfo.td | 6 ++++--
ARMRegisterInfo.cpp | 2 +-
5 files changed, 14 insertions(+), 51 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.13 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.14
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.13 Tue Jun 27 16:52:45 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Sun Jul 9 20:41:35 2006
@@ -95,8 +95,7 @@
// If the argument is actually used, emit a load from the right stack
// slot.
if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
- //hack
- unsigned ArgOffset = 0;
+ unsigned ArgOffset = (ArgNo - num_regs) * 4;
MachineFrameInfo *MFI = MF.getFrameInfo();
unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
@@ -165,6 +164,7 @@
void Select(SDOperand &Result, SDOperand Op);
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+ bool SelectAddrReg(SDOperand N, SDOperand &Base);
// Include the pieces autogenerated from the target description.
#include "ARMGenDAGISel.inc"
@@ -183,12 +183,13 @@
ScheduleAndEmitDAG(DAG);
}
-static void SelectFrameIndex(SelectionDAG *CurDAG, SDOperand &Result, SDNode *N, SDOperand Op) {
- int FI = cast<FrameIndexSDNode>(N)->getIndex();
-
- SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
-
- Result = CurDAG->SelectNodeTo(N, ARM::movri, Op.getValueType(), TFI);
+bool ARMDAGToDAGISel::SelectAddrReg(SDOperand N, SDOperand &Base) {
+ if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
+ Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
+ }
+ else
+ Base = N;
+ return true; //any address fits in a register
}
void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
@@ -198,10 +199,6 @@
default:
SelectCode(Result, Op);
break;
-
- case ISD::FrameIndex:
- SelectFrameIndex(CurDAG, Result, N, Op);
- break;
}
}
Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.3 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.4
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.3 Tue Jun 27 16:52:45 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp Sun Jul 9 20:41:35 2006
@@ -41,25 +41,3 @@
return true;
}
}
-
-/// isLoadFromStackSlot - If the specified machine instruction is a direct
-/// load from a stack slot, return the virtual or physical register number of
-/// the destination along with the FrameIndex of the loaded stack slot. If
-/// not, return 0. This predicate must return 0 if the instruction has
-/// any side effects other than loading from the stack slot.
-unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
- int &FrameIndex) const {
- assert(0 && "not implemented");
- return 0;
-}
-
-/// isStoreToStackSlot - If the specified machine instruction is a direct
-/// store to a stack slot, return the virtual or physical register number of
-/// the source reg along with the FrameIndex of the loaded stack slot. If
-/// not, return 0. This predicate must return 0 if the instruction has
-/// any side effects other than storing to the stack slot.
-unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI,
- int &FrameIndex) const {
- assert(0 && "not implemented");
- return 0;
-}
Index: llvm/lib/Target/ARM/ARMInstrInfo.h
diff -u llvm/lib/Target/ARM/ARMInstrInfo.h:1.1 llvm/lib/Target/ARM/ARMInstrInfo.h:1.2
--- llvm/lib/Target/ARM/ARMInstrInfo.h:1.1 Sun May 14 17:18:28 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.h Sun Jul 9 20:41:35 2006
@@ -36,20 +36,6 @@
///
virtual bool isMoveInstr(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg) const;
-
- /// isLoadFromStackSlot - If the specified machine instruction is a direct
- /// load from a stack slot, return the virtual or physical register number of
- /// the destination along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return 0 if the instruction has
- /// any side effects other than loading from the stack slot.
- virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
-
- /// isStoreToStackSlot - If the specified machine instruction is a direct
- /// store to a stack slot, return the virtual or physical register number of
- /// the source reg along with the FrameIndex of the loaded stack slot. If
- /// not, return 0. This predicate must return 0 if the instruction has
- /// any side effects other than storing to the stack slot.
- virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
};
}
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.5 llvm/lib/Target/ARM/ARMInstrInfo.td:1.6
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.5 Sat Jun 17 19:08:07 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Sun Jul 9 20:41:35 2006
@@ -12,7 +12,9 @@
//
//===----------------------------------------------------------------------===//
-
+// Define ARM specific addressing mode.
+ //register or frame index
+def raddr : ComplexPattern<iPTR, 1, "SelectAddrReg", []>;
//===----------------------------------------------------------------------===//
// Instructions
@@ -42,7 +44,7 @@
def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldr $dst, [$addr]",
- [(set IntRegs:$dst, (load IntRegs:$addr))]>;
+ [(set IntRegs:$dst, (load raddr:$addr))]>;
def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
"str $src, [$addr]",
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.5 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.6
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.5 Tue Jun 27 16:52:45 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Sun Jul 9 20:41:35 2006
@@ -81,7 +81,7 @@
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
- assert (MI.getOpcode() == ARM::movri);
+ assert (MI.getOpcode() == ARM::ldr);
unsigned FrameIdx = 1;
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