[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp PPCCodeEmitter.cpp PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCBranchSelector.cpp updated: 1.23 -> 1.24
PPCCodeEmitter.cpp updated: 1.59 -> 1.60
PPCISelLowering.cpp updated: 1.194 -> 1.195
PPCInstr64Bit.td updated: 1.12 -> 1.13
PPCInstrInfo.td updated: 1.235 -> 1.236
---
Log message:

Implement 64-bit undef, sub, shl/shr, srem/urem


---
Diffs of the changes:  (+23 -6)

 PPCBranchSelector.cpp |    3 ++-
 PPCCodeEmitter.cpp    |    3 ++-
 PPCISelLowering.cpp   |    2 ++
 PPCInstr64Bit.td      |   19 ++++++++++++++++---
 PPCInstrInfo.td       |    2 +-
 5 files changed, 23 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.23 llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.24
--- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.23	Thu May  4 12:21:19 2006
+++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp	Tue Jun 27 13:18:40 2006
@@ -52,7 +52,8 @@
     // minor pessimization that saves us from having to worry about
     // keeping the offsets up to date later when we emit long branch glue.
     return 8;
-  case PPC::IMPLICIT_DEF_GPR: // no asm emitted
+  case PPC::IMPLICIT_DEF_GPRC: // no asm emitted
+  case PPC::IMPLICIT_DEF_G8RC: // no asm emitted
   case PPC::IMPLICIT_DEF_F4: // no asm emitted
   case PPC::IMPLICIT_DEF_F8: // no asm emitted
     return 0;


Index: llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.59 llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.60
--- llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:1.59	Wed May  3 15:30:20 2006
+++ llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp	Tue Jun 27 13:18:40 2006
@@ -125,7 +125,8 @@
     default:
       MCE.emitWordBE(getBinaryCodeForInstr(*I));
       break;
-    case PPC::IMPLICIT_DEF_GPR:
+    case PPC::IMPLICIT_DEF_GPRC:
+    case PPC::IMPLICIT_DEF_G8RC:
     case PPC::IMPLICIT_DEF_F8:
     case PPC::IMPLICIT_DEF_F4:
     case PPC::IMPLICIT_DEF_VRRC:


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.194 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.195
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.194	Tue Jun 27 12:34:57 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Tue Jun 27 13:18:41 2006
@@ -58,6 +58,8 @@
   // PowerPC has no SREM/UREM instructions
   setOperationAction(ISD::SREM, MVT::i32, Expand);
   setOperationAction(ISD::UREM, MVT::i32, Expand);
+  setOperationAction(ISD::SREM, MVT::i64, Expand);
+  setOperationAction(ISD::UREM, MVT::i64, Expand);
   
   // We don't support sin/cos/sqrt/fmod
   setOperationAction(ISD::FSIN , MVT::f64, Expand);


Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.12 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.13
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.12	Tue Jun 27 12:30:08 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td	Tue Jun 27 13:18:41 2006
@@ -54,6 +54,14 @@
 
 
 //===----------------------------------------------------------------------===//
+// Pseudo instructions.
+//
+
+def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; $rD = IMPLICIT_DEF_G8RC",
+                              [(set G8RC:$rD, (undef))]>;
+
+
+//===----------------------------------------------------------------------===//
 // Fixed point instructions.
 //
 
@@ -134,7 +142,12 @@
                      "addis $rD, $rA, $imm", IntGeneral,
                      [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
 
-
+def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
+                     "subfic $rD, $rA, $imm", IntGeneral,
+                     [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
+def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
+                     "subf $rT, $rA, $rB", IntGeneral,
+                     [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
 
 
 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
@@ -326,9 +339,9 @@
           (OR8To4 G8RC:$in, G8RC:$in)>;
 
 // SHL/SRL
-def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
+def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
           (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
-def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
+def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
           (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
 
 // Hi and Lo for Darwin Global Addresses.


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.235 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.236
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.235	Mon Jun 26 19:04:13 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Tue Jun 27 13:18:41 2006
@@ -252,7 +252,7 @@
 def UPDATE_VRSAVE    : Pseudo<(ops GPRC:$rD, GPRC:$rS),
                               "UPDATE_VRSAVE $rD, $rS", []>;
 }
-def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
+def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
                               [(set GPRC:$rD, (undef))]>;
 def IMPLICIT_DEF_F8  : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
                               [(set F8RC:$rD, (undef))]>;