[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td ARMRegisterInfo.cpp ARMRegisterInfo.td

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.4 -> 1.5
ARMRegisterInfo.cpp updated: 1.3 -> 1.4
ARMRegisterInfo.td updated: 1.1 -> 1.2
---
Log message:

initial implementation of ARMRegisterInfo::eliminateFrameIndex
fixes test/Regression/CodeGen/ARM/ret_arg5.ll



---
Diffs of the changes:  (+34 -2)

 ARMInstrInfo.td     |    4 ++++
 ARMRegisterInfo.cpp |   24 +++++++++++++++++++++++-
 ARMRegisterInfo.td  |    8 +++++++-
 3 files changed, 34 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.4 llvm/lib/Target/ARM/ARMInstrInfo.td:1.5
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.4	Tue May 30 12:33:19 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Sat Jun 17 19:08:07 2006
@@ -53,3 +53,7 @@
 
 def movri   : InstARM<(ops IntRegs:$dst, i32imm:$src),
                        "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
+
+def addri   : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
+                       "add $dst, $a, $b",
+		       [(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.3 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.4
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.3	Thu May 18 16:45:49 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Sat Jun 17 19:08:07 2006
@@ -77,7 +77,29 @@
 
 void
 ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
-  assert(0 && "Not Implemented");
+  MachineInstr &MI = *II;
+  MachineBasicBlock &MBB = *MI.getParent();
+  MachineFunction &MF = *MBB.getParent();
+
+  assert (MI.getOpcode() == ARM::movrr);
+
+  unsigned FrameIdx = 1;
+
+  int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
+
+  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
+
+  unsigned StackSize = MF.getFrameInfo()->getStackSize();
+
+  Offset += StackSize;
+
+  // Insert a set of r12 with the full address
+  // r12 = r13 + offset
+  MachineBasicBlock *MBB2 = MI.getParent();
+  BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
+
+  // Replace the FrameIndex with r12
+  MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
 }
 
 void ARMRegisterInfo::


Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.1 llvm/lib/Target/ARM/ARMRegisterInfo.td:1.2
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.1	Sun May 14 17:18:28 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td	Sat Jun 17 19:08:07 2006
@@ -50,7 +50,13 @@
   let MethodBodies = [{
     IntRegsClass::iterator
     IntRegsClass::allocation_order_end(MachineFunction &MF) const {
-      return end() - 1;
+      // r15 == Program Counter
+      // r14 == Link Register
+      // r13 == Stack Pointer
+      // r12 == ip (scratch)
+      // r11 == Frame Pointer
+      // r10 == Stack Limit
+      return end() - 4;
     }
   }];
 }