[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td
Evan Cheng
evan.cheng at apple.com
Thu Jun 15 01:15:07 PDT 2006
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.229 -> 1.230
X86InstrSSE.td updated: 1.122 -> 1.123
---
Log message:
Type of vector extract / insert index operand should be iPTR.
---
Diffs of the changes: (+18 -18)
X86ISelLowering.cpp | 10 +++++-----
X86InstrSSE.td | 26 +++++++++++++-------------
2 files changed, 18 insertions(+), 18 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.229 llvm/lib/Target/X86/X86ISelLowering.cpp:1.230
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.229 Wed Jun 14 13:17:40 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Thu Jun 15 03:14:54 2006
@@ -2784,7 +2784,7 @@
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
Vec, Vec, Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
- DAG.getConstant(0, MVT::i32));
+ DAG.getConstant(0, getPointerTy()));
} else if (MVT::getSizeInBits(VT) == 64) {
SDOperand Vec = Op.getOperand(0);
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
@@ -2802,7 +2802,7 @@
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
- DAG.getConstant(0, MVT::i32));
+ DAG.getConstant(0, getPointerTy()));
}
return SDOperand();
@@ -2848,15 +2848,15 @@
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
- DAG.getConstant(0, MVT::i32));
+ DAG.getConstant(0, getPointerTy()));
}
}
N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
- DAG.getConstant(Idx, MVT::i32));
+ DAG.getConstant(Idx, getPointerTy()));
N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
- DAG.getConstant(Idx+1, MVT::i32));
+ DAG.getConstant(Idx+1, getPointerTy()));
return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
}
}
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.122 llvm/lib/Target/X86/X86InstrSSE.td:1.123
--- llvm/lib/Target/X86/X86InstrSSE.td:1.122 Wed May 31 14:00:07 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Thu Jun 15 03:14:54 2006
@@ -811,11 +811,11 @@
def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
"movlps {$src, $dst|$dst, $src}",
[(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
- (i32 0))), addr:$dst)]>;
+ (iPTR 0))), addr:$dst)]>;
def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
"movlpd {$src, $dst|$dst, $src}",
[(store (f64 (vector_extract (v2f64 VR128:$src),
- (i32 0))), addr:$dst)]>;
+ (iPTR 0))), addr:$dst)]>;
// v2f64 extract element 1 is always custom lowered to unpack high to low
// and extract element 0 so the non-store version isn't too horrible.
@@ -824,13 +824,13 @@
[(store (f64 (vector_extract
(v2f64 (vector_shuffle
(bc_v2f64 (v4f32 VR128:$src)), (undef),
- UNPCKH_shuffle_mask)), (i32 0))),
+ UNPCKH_shuffle_mask)), (iPTR 0))),
addr:$dst)]>;
def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
"movhpd {$src, $dst|$dst, $src}",
[(store (f64 (vector_extract
(v2f64 (vector_shuffle VR128:$src, (undef),
- UNPCKH_shuffle_mask)), (i32 0))),
+ UNPCKH_shuffle_mask)), (iPTR 0))),
addr:$dst)]>;
let isTwoAddress = 1 in {
@@ -2020,14 +2020,14 @@
(ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
- GR32:$src2, (i32 imm:$src3))))]>;
+ GR32:$src2, (iPTR imm:$src3))))]>;
def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
(v8i16 (X86pinsrw (v8i16 VR128:$src1),
(i32 (anyext (loadi16 addr:$src2))),
- (i32 imm:$src3))))]>;
+ (iPTR imm:$src3))))]>;
}
//===----------------------------------------------------------------------===//
@@ -2166,32 +2166,32 @@
// FIXME: may not be able to eliminate this movss with coalescing the src and
// dest register classes are different. We really want to write this pattern
// like this:
-// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))),
+// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
// (f32 FR32:$src)>;
def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
"movss {$src, $dst|$dst, $src}",
[(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
- (i32 0)))]>;
+ (iPTR 0)))]>;
def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
"movss {$src, $dst|$dst, $src}",
[(store (f32 (vector_extract (v4f32 VR128:$src),
- (i32 0))), addr:$dst)]>;
+ (iPTR 0))), addr:$dst)]>;
def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
"movsd {$src, $dst|$dst, $src}",
[(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
- (i32 0)))]>;
+ (iPTR 0)))]>;
def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
"movsd {$src, $dst|$dst, $src}",
[(store (f64 (vector_extract (v2f64 VR128:$src),
- (i32 0))), addr:$dst)]>;
+ (iPTR 0))), addr:$dst)]>;
def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
"movd {$src, $dst|$dst, $src}",
[(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
- (i32 0)))]>;
+ (iPTR 0)))]>;
def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
"movd {$src, $dst|$dst, $src}",
[(store (i32 (vector_extract (v4i32 VR128:$src),
- (i32 0))), addr:$dst)]>;
+ (iPTR 0))), addr:$dst)]>;
// Move to lower bits of a VR128, leaving upper bits alone.
// Three operand (but two address) aliases.
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