[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.228 -> 1.229
---
Log message:

Add argument registers to the end of call operand list (partial fix).

---
Diffs of the changes:  (+15 -1)

 X86ISelLowering.cpp |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.228 llvm/lib/Target/X86/X86ISelLowering.cpp:1.229
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.228	Fri Jun  9 01:24:42 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Wed Jun 14 13:17:40 2006
@@ -617,6 +617,13 @@
   std::vector<SDOperand> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
+
+  // Add argument registers to the end of the list so that they are known live
+  // into the call.
+  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
+    Ops.push_back(DAG.getRegister(RegsToPass[i].first, 
+                                  RegsToPass[i].second.getValueType()));
+
   if (InFlag.Val)
     Ops.push_back(InFlag);
 
@@ -985,7 +992,7 @@
   return DAG.getNode(ISD::MERGE_VALUES, RetVTs, ArgValues);
 }
 
- SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG) {
+SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG) {
   SDOperand Chain     = Op.getOperand(0);
   unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
   bool isVarArg       = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
@@ -1139,6 +1146,13 @@
   std::vector<SDOperand> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
+
+  // Add argument registers to the end of the list so that they are known live
+  // into the call.
+  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
+    Ops.push_back(DAG.getRegister(RegsToPass[i].first, 
+                                  RegsToPass[i].second.getValueType()));
+
   if (InFlag.Val)
     Ops.push_back(InFlag);