[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.180 -> 1.181
---
Log message:

Handle SETO* like we handle SET*, restoring behavior after Evan's setcc
change.  This fixes PowerPC/fnegsel.ll.



---
Diffs of the changes:  (+8 -0)

 PPCISelLowering.cpp |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.180 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.181
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.180	Wed May 17 14:00:46 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Tue May 23 19:06:44 2006
@@ -1216,17 +1216,21 @@
     switch (CC) {
     default: break;       // SETUO etc aren't handled by fsel.
     case ISD::SETULT:
+    case ISD::SETOLT:
     case ISD::SETLT:
       std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
     case ISD::SETUGE:
+    case ISD::SETOGE:
     case ISD::SETGE:
       if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
         LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
       return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
     case ISD::SETUGT:
+    case ISD::SETOGT:
     case ISD::SETGT:
       std::swap(TV, FV);  // fsel is natively setge, swap operands for setlt
     case ISD::SETULE:
+    case ISD::SETOLE:
     case ISD::SETLE:
       if (LHS.getValueType() == MVT::f32)   // Comparison is always 64-bits
         LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
@@ -1238,24 +1242,28 @@
   switch (CC) {
   default: break;       // SETUO etc aren't handled by fsel.
   case ISD::SETULT:
+  case ISD::SETOLT:
   case ISD::SETLT:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
   case ISD::SETUGE:
+  case ISD::SETOGE:
   case ISD::SETGE:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
   case ISD::SETUGT:
+  case ISD::SETOGT:
   case ISD::SETGT:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits
       Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
       return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
   case ISD::SETULE:
+  case ISD::SETOLE:
   case ISD::SETLE:
     Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
     if (Cmp.getValueType() == MVT::f32)   // Comparison is always 64-bits