[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.372 -> 1.373
---
Log message:

Merge identical code.


---
Diffs of the changes:  (+0 -8)

 LegalizeDAG.cpp |    8 --------
 1 files changed, 8 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.372 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.373
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.372	Tue May  9 13:20:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri May 12 21:11:14 2006
@@ -3012,14 +3012,6 @@
   case ISD::AND:
   case ISD::OR:
   case ISD::XOR:
-    // The input may have strange things in the top bits of the registers, but
-    // these operations don't care.  They may have weird bits going out, but
-    // that too is okay if they are integer operations.
-    Tmp1 = PromoteOp(Node->getOperand(0));
-    Tmp2 = PromoteOp(Node->getOperand(1));
-    assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
-    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
-    break;
   case ISD::ADD:
   case ISD::SUB:
   case ISD::MUL: