[llvm-commits] CVS: llvm/lib/Target/TargetLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target:

TargetLowering.cpp updated: 1.60 -> 1.61
---
Log message:

When tracking demanded bits, if any bits from the sext of an SRA are demanded,
then so is the input sign bit.  This fixes mediabench/g721 on X86.


---
Diffs of the changes:  (+8 -2)

 TargetLowering.cpp |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/TargetLowering.cpp
diff -u llvm/lib/Target/TargetLowering.cpp:1.60 llvm/lib/Target/TargetLowering.cpp:1.61
--- llvm/lib/Target/TargetLowering.cpp:1.60	Sat May  6 18:48:13 2006
+++ llvm/lib/Target/TargetLowering.cpp	Mon May  8 12:22:53 2006
@@ -467,8 +467,14 @@
       HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
       uint64_t TypeMask = MVT::getIntVTBitMask(VT);
       
-      if (SimplifyDemandedBits(Op.getOperand(0),
-                               (DemandedMask << ShAmt) & TypeMask,
+      uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
+
+      // If any of the demanded bits are produced by the sign extension, we also
+      // demand the input sign bit.
+      if (HighBits & DemandedMask)
+        InDemandedMask |= MVT::getIntVTSignBit(VT);
+      
+      if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
                                KnownZero, KnownOne, TLO, Depth+1))
         return true;
       assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");