[llvm-commits] CVS: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp MachineInstr.cpp RegAllocLocal.cpp RegAllocSimple.cpp TwoAddressInstructionPass.cpp VirtRegMap.cpp
Chris Lattner
lattner at cs.uiuc.edu
Thu May 4 10:52:42 PDT 2006
Changes in directory llvm/lib/CodeGen:
LiveIntervalAnalysis.cpp updated: 1.156 -> 1.157
MachineInstr.cpp updated: 1.117 -> 1.118
RegAllocLocal.cpp updated: 1.77 -> 1.78
RegAllocSimple.cpp updated: 1.66 -> 1.67
TwoAddressInstructionPass.cpp updated: 1.32 -> 1.33
VirtRegMap.cpp updated: 1.65 -> 1.66
---
Log message:
Move some methods out of MachineInstr into MachineOperand
---
Diffs of the changes: (+16 -35)
LiveIntervalAnalysis.cpp | 6 +++---
MachineInstr.cpp | 19 -------------------
RegAllocLocal.cpp | 6 +++---
RegAllocSimple.cpp | 2 +-
TwoAddressInstructionPass.cpp | 2 +-
VirtRegMap.cpp | 16 ++++++++--------
6 files changed, 16 insertions(+), 35 deletions(-)
Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.156 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.157
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.156 Mon May 1 16:16:03 2006
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Thu May 4 12:52:23 2006
@@ -187,7 +187,7 @@
MRegisterInfo::isVirtualRegister(mop.getReg())) {
// replace register with representative register
unsigned reg = rep(mop.getReg());
- mii->SetMachineOperandReg(i, reg);
+ mii->getOperand(i).setReg(reg);
LiveInterval &RegInt = getInterval(reg);
RegInt.weight +=
@@ -263,7 +263,7 @@
if (NewRegLiveIn && mop.isUse()) {
// We already emitted a reload of this value, reuse it for
// subsequent operands.
- MI->SetMachineOperandReg(i, NewRegLiveIn);
+ MI->getOperand(i).setReg(NewRegLiveIn);
DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
<< " for operand #" << i << '\n');
} else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
@@ -300,7 +300,7 @@
// create a new register for this spill
NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
- MI->SetMachineOperandReg(i, NewRegLiveIn);
+ MI->getOperand(i).setReg(NewRegLiveIn);
vrm.grow();
vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.117 llvm/lib/CodeGen/MachineInstr.cpp:1.118
--- llvm/lib/CodeGen/MachineInstr.cpp:1.117 Thu May 4 12:21:19 2006
+++ llvm/lib/CodeGen/MachineInstr.cpp Thu May 4 12:52:23 2006
@@ -107,25 +107,6 @@
return false;
}
-void
-MachineInstr::SetMachineOperandConst(unsigned i,
- MachineOperand::MachineOperandType opTy,
- int intValue) {
- assert(i < getNumOperands());
- operands[i].opType = opTy;
- operands[i].contents.immedVal = intValue;
- operands[i].extra.regNum = -1;
- operands[i].flags = 0;
-}
-
-void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
- assert(i < getNumOperands());
-
- operands[i].opType = MachineOperand::MO_VirtualRegister;
- operands[i].contents.GV = NULL;
- operands[i].extra.regNum = regNum;
-}
-
void MachineInstr::dump() const {
std::cerr << " " << *this;
}
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.77 llvm/lib/CodeGen/RegAllocLocal.cpp:1.78
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.77 Sun Jan 22 17:39:54 2006
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Thu May 4 12:52:23 2006
@@ -443,7 +443,7 @@
// and return.
if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
MarkPhysRegRecentlyUsed(PR); // Already have this value available!
- MI->SetMachineOperandReg(OpNum, PR); // Assign the input register
+ MI->getOperand(OpNum).setReg(PR); // Assign the input register
return MI;
}
@@ -481,7 +481,7 @@
++NumLoads; // Update statistics
PhysRegsEverUsed[PhysReg] = true;
- MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register
+ MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
return MI;
}
@@ -599,7 +599,7 @@
DestPhysReg = getReg(MBB, MI, DestVirtReg);
PhysRegsEverUsed[DestPhysReg] = true;
markVirtRegModified(DestVirtReg);
- MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
+ MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
}
}
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.66 llvm/lib/CodeGen/RegAllocSimple.cpp:1.67
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.66 Sun Jan 22 17:39:54 2006
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Thu May 4 12:52:23 2006
@@ -211,7 +211,7 @@
Virt2PhysRegMap[virtualReg] = physReg;
}
}
- MI->SetMachineOperandReg(i, physReg);
+ MI->getOperand(i).setReg(physReg);
DEBUG(std::cerr << "virt: " << virtualReg <<
", phys: " << op.getReg() << "\n");
}
Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.32 llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.33
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.32 Sun Jan 22 17:41:00 2006
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp Thu May 4 12:52:23 2006
@@ -200,7 +200,7 @@
for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
if (mi->getOperand(i).isRegister() &&
mi->getOperand(i).getReg() == regB)
- mi->SetMachineOperandReg(i, regA);
+ mi->getOperand(i).setReg(regA);
}
}
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.65 llvm/lib/CodeGen/VirtRegMap.cpp:1.66
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.65 Mon May 1 17:03:24 2006
+++ llvm/lib/CodeGen/VirtRegMap.cpp Thu May 4 12:52:23 2006
@@ -182,7 +182,7 @@
}
}
PhysRegsUsed[PhysReg] = true;
- MI.SetMachineOperandReg(i, PhysReg);
+ MI.getOperand(i).setReg(PhysReg);
} else {
PhysRegsUsed[MO.getReg()] = true;
}
@@ -458,7 +458,7 @@
// Any stores to this stack slot are not dead anymore.
MaybeDeadStores.erase(NewOp.StackSlot);
- MI->SetMachineOperandReg(NewOp.Operand, NewPhysReg);
+ MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
++NumLoads;
@@ -536,7 +536,7 @@
// This virtual register was assigned a physreg!
unsigned Phys = VRM.getPhys(VirtReg);
PhysRegsUsed[Phys] = true;
- MI.SetMachineOperandReg(i, Phys);
+ MI.getOperand(i).setReg(Phys);
continue;
}
@@ -567,7 +567,7 @@
<< MRI->getName(PhysReg) << " for vreg"
<< VirtReg <<" instead of reloading into physreg "
<< MRI->getName(VRM.getPhys(VirtReg)) << "\n");
- MI.SetMachineOperandReg(i, PhysReg);
+ MI.getOperand(i).setReg(PhysReg);
// The only technical detail we have is that we don't know that
// PhysReg won't be clobbered by a reloaded stack slot that occurs
@@ -618,7 +618,7 @@
<< MRI->getName(PhysReg) << " for vreg"
<< VirtReg
<< " instead of reloading into same physreg.\n");
- MI.SetMachineOperandReg(i, PhysReg);
+ MI.getOperand(i).setReg(PhysReg);
++NumReused;
continue;
}
@@ -633,7 +633,7 @@
Spills.ClobberPhysReg(DesignatedReg);
Spills.addAvailable(StackSlot, DesignatedReg);
- MI.SetMachineOperandReg(i, DesignatedReg);
+ MI.getOperand(i).setReg(DesignatedReg);
DEBUG(std::cerr << '\t' << *prior(MII));
++NumReused;
continue;
@@ -662,7 +662,7 @@
MaybeDeadStores.erase(StackSlot);
Spills.addAvailable(StackSlot, PhysReg);
++NumLoads;
- MI.SetMachineOperandReg(i, PhysReg);
+ MI.getOperand(i).setReg(PhysReg);
DEBUG(std::cerr << '\t' << *prior(MII));
}
@@ -817,7 +817,7 @@
PhysRegsUsed[PhysReg] = true;
MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
DEBUG(std::cerr << "Store:\t" << *next(MII));
- MI.SetMachineOperandReg(i, PhysReg);
+ MI.getOperand(i).setReg(PhysReg);
// Check to see if this is a noop copy. If so, eliminate the
// instruction before considering the dest reg to be changed.
More information about the llvm-commits
mailing list