[llvm-commits] CVS: llvm/lib/Target/X86/README.txt X86ISelLowering.cpp X86InstrSSE.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

README.txt updated: 1.88 -> 1.89
X86ISelLowering.cpp updated: 1.167 -> 1.168
X86InstrSSE.td updated: 1.91 -> 1.92
---
Log message:

Silly bug

---
Diffs of the changes:  (+11 -18)

 README.txt          |    5 -----
 X86ISelLowering.cpp |   22 ++++++++++------------
 X86InstrSSE.td      |    2 +-
 3 files changed, 11 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/X86/README.txt
diff -u llvm/lib/Target/X86/README.txt:1.88 llvm/lib/Target/X86/README.txt:1.89
--- llvm/lib/Target/X86/README.txt:1.88	Fri Apr 14 02:24:04 2006
+++ llvm/lib/Target/X86/README.txt	Sat Apr 15 00:37:34 2006
@@ -810,8 +810,3 @@
 How about andps, andpd, and pand? Do we really care about the type of the packed
 elements? If not, why not always use the "ps" variants which are likely to be
 shorter.
-
-//===---------------------------------------------------------------------===//
-
-Make sure XMM registers are spilled to 128-bit locations (if not already) and
-add vector SSE opcodes to X86RegisterInfo::foldMemoryOperand().


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.167 llvm/lib/Target/X86/X86ISelLowering.cpp:1.168
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.167	Fri Apr 14 22:13:24 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Sat Apr 15 00:37:34 2006
@@ -1724,27 +1724,26 @@
     return false;
 
   // Expect 1, 1, 3, 3
-  unsigned NumNodes = 0;
   for (unsigned i = 0; i < 2; ++i) {
     SDOperand Arg = N->getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) continue;
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
     unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val != 1) return false;
-    NumNodes++;
   }
+
+  bool HasHi = false;
   for (unsigned i = 2; i < 4; ++i) {
     SDOperand Arg = N->getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) continue;
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
     unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val != 3) return false;
-    NumNodes++;
+    HasHi = true;
   }
 
-  // Don't use movshdup if the resulting vector contains only one undef node.
-  // Use {p}shuf* instead.
-  return NumNodes > 1;
+  // Don't use movshdup if it can be done with a shufps.
+  return HasHi;
 }
 
 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
@@ -1756,27 +1755,26 @@
     return false;
 
   // Expect 0, 0, 2, 2
-  unsigned NumNodes = 0;
   for (unsigned i = 0; i < 2; ++i) {
     SDOperand Arg = N->getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) continue;
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
     unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val != 0) return false;
-    NumNodes++;
   }
+
+  bool HasHi = false;
   for (unsigned i = 2; i < 4; ++i) {
     SDOperand Arg = N->getOperand(i);
     if (Arg.getOpcode() == ISD::UNDEF) continue;
     assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
     unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
     if (Val != 2) return false;
-    NumNodes++;
+    HasHi = true;
   }
 
-  // Don't use movsldup if the resulting vector contains only one undef node.
-  // Use {p}shuf* instead.
-  return NumNodes > 1;
+  // Don't use movshdup if it can be done with a shufps.
+  return HasHi;
 }
 
 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.91 llvm/lib/Target/X86/X86InstrSSE.td:1.92
--- llvm/lib/Target/X86/X86InstrSSE.td:1.91	Fri Apr 14 18:32:40 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Sat Apr 15 00:37:34 2006
@@ -169,7 +169,7 @@
 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
 // S3I - SSE3 instructions with TB and OpSize prefixes.
 // S3SI - SSE3 instructions with XS prefix.
-// S3SI - SSE3 instructions with XD prefix.
+// S3DI - SSE3 instructions with XD prefix.
 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
       : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>