[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrSSE.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86InstrSSE.td updated: 1.74 -> 1.75
---
Log message:

Misc. intrinsics.


---
Diffs of the changes:  (+13 -13)

 X86InstrSSE.td |   26 +++++++++++++-------------
 1 files changed, 13 insertions(+), 13 deletions(-)


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.74 llvm/lib/Target/X86/X86InstrSSE.td:1.75
--- llvm/lib/Target/X86/X86InstrSSE.td:1.74	Tue Apr 11 01:57:30 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Apr 11 12:35:57 2006
@@ -1516,18 +1516,18 @@
                  Imp<[EDI],[]>;
 
 // Prefetching loads
-def PREFETCHT0   : I<0x18, MRM1m, (ops i8mem:$src),
-                     "prefetcht0 $src", []>, TB,
-                   Requires<[HasSSE1]>;
-def PREFETCHT1   : I<0x18, MRM2m, (ops i8mem:$src),
-                     "prefetcht0 $src", []>, TB,
-                   Requires<[HasSSE1]>;
-def PREFETCHT2   : I<0x18, MRM3m, (ops i8mem:$src),
-                     "prefetcht0 $src", []>, TB,
-                   Requires<[HasSSE1]>;
-def PREFETCHTNTA : I<0x18, MRM0m, (ops i8mem:$src),
-                     "prefetcht0 $src", []>, TB,
-                   Requires<[HasSSE1]>;
+def PREFETCHT0   : PSI<0x18, MRM1m, (ops i8mem:$src),
+                       "prefetcht0 $src",
+                       [(int_x86_sse_prefetch addr:$src, 1)]>;
+def PREFETCHT1   : PSI<0x18, MRM2m, (ops i8mem:$src),
+                       "prefetcht1 $src",
+                       [(int_x86_sse_prefetch addr:$src, 2)]>;
+def PREFETCHT2   : PSI<0x18, MRM3m, (ops i8mem:$src),
+                       "prefetcht2 $src",
+                       [(int_x86_sse_prefetch addr:$src, 3)]>;
+def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
+                       "prefetchtnta $src",
+                       [(int_x86_sse_prefetch addr:$src, 0)]>;
 
 // Non-temporal stores
 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
@@ -1546,7 +1546,7 @@
 
 // Store fence
 def SFENCE : I<0xAE, MRM7m, (ops),
-               "sfence", []>, TB, Requires<[HasSSE1]>;
+               "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
 
 // MXCSR register
 def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),