[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td PPCInstrFormats.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrAltivec.td updated: 1.36 -> 1.37
PPCInstrFormats.td updated: 1.71 -> 1.72
---
Log message:

Add m[tf]vscr instructions.


---
Diffs of the changes:  (+34 -0)

 PPCInstrAltivec.td |    7 +++++++
 PPCInstrFormats.td |   27 +++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.36 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.37
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.36	Tue Apr  4 18:43:56 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td	Tue Apr  4 19:03:57 2006
@@ -93,6 +93,13 @@
 def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC",
                                [(set VRRC:$rD, (v4f32 (undef)))]>;
 
+def MFVSCR : VXForm_4<1540, (ops VRRC:$vD),
+                      "mfvcr $vD", LdStGeneral,
+                      [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; 
+def MTVSCR : VXForm_5<1604, (ops VRRC:$vB),
+                      "mtvcr $vB", LdStGeneral,
+                      [(int_ppc_altivec_mtvscr VRRC:$vB)]>; 
+
 let isLoad = 1, PPC970_Unit = 2 in {  // Loads.
 def LVEBX: XForm_1<31,   7, (ops VRRC:$vD, memrr:$src),
                    "lvebx $vD, $src", LdStGeneral,


Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.71 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.72
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.71	Sun Mar 26 21:34:17 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td	Tue Apr  4 19:03:57 2006
@@ -697,6 +697,33 @@
   let Inst{21-31} = xo;
 }
 
+/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
+class VXForm_4<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
+class VXForm_5<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VB;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = 0;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
 
 // E-4 VXR-Form
 class VXRForm_1<bits<10> xo, dag OL, string asmstr,