[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.137 -> 1.138
---
Log message:

Constant fold all of the vector binops.  This allows us to compile this:

"vector unsigned char mergeLowHigh = (vector unsigned char) 
( 8, 9, 10, 11, 16, 17, 18, 19, 12, 13, 14, 15, 20, 21, 22, 23 );
vector unsigned char mergeHighLow = vec_xor( mergeLowHigh, vec_splat_u8(8));"

aka:

void %test2(<16 x sbyte>* %P) {
  store <16 x sbyte> cast (<4 x int> xor (<4 x int> cast (<16 x ubyte> < ubyte 8, ubyte 9, ubyte 10, ubyte 11, ubyte 16, ubyte 17, ubyte 18, ubyte 19, ubyte 12, ubyte 13, ubyte 14, ubyte 15, ubyte 20, ubyte 21, ubyte 22, ubyte 23 > to <4 x int>), <4 x int> cast (<16 x sbyte> < sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8, sbyte 8 > to <4 x int>)) to <16 x sbyte>), <16 x sbyte> * %P
  ret void
}

into this:

_test2:
        mfspr r2, 256
        oris r4, r2, 32768
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
        li r4, lo16(LCPI2_0)
        lis r5, ha16(LCPI2_0)
        lvx v0, r5, r4
        stvx v0, 0, r3
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr

instead of this:

_test2:
        mfspr r2, 256
        oris r4, r2, 49152
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r4
        li r4, lo16(LCPI2_0)
        lis r5, ha16(LCPI2_0)
        vspltisb v0, 8
        lvx v1, r5, r4
        vxor v0, v1, v0
        stvx v0, 0, r3
        mtspr 256: http://llvm.cs.uiuc.edu/PR256 , r2
        blr

... which occurs here:
http://developer.apple.com/hardware/ve/calcspeed.html



---
Diffs of the changes:  (+49 -0)

 DAGCombiner.cpp |   49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 49 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.137 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.138
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.137	Sat Apr  1 20:53:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Sat Apr  1 21:25:57 2006
@@ -176,6 +176,7 @@
     SDOperand visitAND(SDNode *N);
     SDOperand visitOR(SDNode *N);
     SDOperand visitXOR(SDNode *N);
+    SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
     SDOperand visitSHL(SDNode *N);
     SDOperand visitSRA(SDNode *N);
     SDOperand visitSRL(SDNode *N);
@@ -656,6 +657,14 @@
   case ISD::VBUILD_VECTOR:      return visitVBUILD_VECTOR(N);
   case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
   case ISD::VVECTOR_SHUFFLE:    return visitVVECTOR_SHUFFLE(N);
+  case ISD::VADD:               return visitVBinOp(N, ISD::ADD , ISD::FADD);
+  case ISD::VSUB:               return visitVBinOp(N, ISD::SUB , ISD::FSUB);
+  case ISD::VMUL:               return visitVBinOp(N, ISD::MUL , ISD::FMUL);
+  case ISD::VSDIV:              return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
+  case ISD::VUDIV:              return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
+  case ISD::VAND:               return visitVBinOp(N, ISD::AND , ISD::AND);
+  case ISD::VOR:                return visitVBinOp(N, ISD::OR  , ISD::OR);
+  case ISD::VXOR:               return visitVBinOp(N, ISD::XOR , ISD::XOR);
   }
   return SDOperand();
 }
@@ -2682,6 +2691,46 @@
   return SDOperand();
 }
 
+/// visitVBinOp - Visit a binary vector operation, like VADD.  IntOp indicates
+/// the scalar operation of the vop if it is operating on an integer vector
+/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
+SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 
+                                   ISD::NodeType FPOp) {
+  MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
+  ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
+  SDOperand LHS = N->getOperand(0);
+  SDOperand RHS = N->getOperand(1);
+  
+  // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
+  // this operation.
+  if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 
+      RHS.getOpcode() == ISD::VBUILD_VECTOR) {
+    std::vector<SDOperand> Ops;
+    for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
+      SDOperand LHSOp = LHS.getOperand(i);
+      SDOperand RHSOp = RHS.getOperand(i);
+      // If these two elements can't be folded, bail out.
+      if ((LHSOp.getOpcode() != ISD::UNDEF &&
+           LHSOp.getOpcode() != ISD::Constant &&
+           LHSOp.getOpcode() != ISD::ConstantFP) ||
+          (RHSOp.getOpcode() != ISD::UNDEF &&
+           RHSOp.getOpcode() != ISD::Constant &&
+           RHSOp.getOpcode() != ISD::ConstantFP))
+        break;
+      Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
+      assert((Ops.back().getOpcode() == ISD::UNDEF ||
+              Ops.back().getOpcode() == ISD::Constant ||
+              Ops.back().getOpcode() == ISD::ConstantFP) &&
+             "Scalar binop didn't fold!");
+    }
+    Ops.push_back(*(LHS.Val->op_end()-2));
+    Ops.push_back(*(LHS.Val->op_end()-1));
+    return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+  }
+  
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
   assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");