[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrAltivec.td PPCInstrFormats.td
Chris Lattner
lattner at cs.uiuc.edu
Sat Mar 25 20:57:30 PST 2006
Changes in directory llvm/lib/Target/PowerPC:
PPCInstrAltivec.td updated: 1.7 -> 1.8
PPCInstrFormats.td updated: 1.68 -> 1.69
---
Log message:
Add all of the altivec comparison instructions. Add patterns for the
non-predicate altivec compare intrinsics.
---
Diffs of the changes: (+108 -5)
PPCInstrAltivec.td | 108 +++++++++++++++++++++++++++++++++++++++++++++++++++--
PPCInstrFormats.td | 5 +-
2 files changed, 108 insertions(+), 5 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.7 llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.8
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.7 Sat Mar 25 20:39:02 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Sat Mar 25 22:57:17 2006
@@ -59,7 +59,10 @@
return PPC::isVecSplatImm(N, 4);
}], VSPLTISW_get_imm>;
-
+class isVDOT { // vector dot instruction.
+ list<Register> Defs = [CR6];
+ bit RC = 1;
+}
//===----------------------------------------------------------------------===//
// Instruction Definitions.
@@ -297,9 +300,108 @@
"vspltisw $vD, $SIMM", VecPerm,
[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
-
-// VX-Form Pseudo Instructions
+// Altivec Comparisons.
+
+// f32 element comparisons.
+def VCMPBFP : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpbfp $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpbfp VRRC:$vA, VRRC:$vB))]>;
+def VCMPBFPo : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpbfp. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPEQFP : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpeqfp $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpeqfp VRRC:$vA, VRRC:$vB))]>;
+def VCMPEQFPo : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpeqfp. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGEFP : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgefp $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgefp VRRC:$vA, VRRC:$vB))]>;
+def VCMPGEFPo : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgefp. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTFP : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtfp $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtfp VRRC:$vA, VRRC:$vB))]>;
+def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtfp. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+
+// i8 element comparisons.
+def VCMPEQUB : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequb $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpequb VRRC:$vA, VRRC:$vB))]>;
+def VCMPEQUBo : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequb. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTSB : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsb $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtsb VRRC:$vA, VRRC:$vB))]>;
+def VCMPGTSBo : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsb. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTUB : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtub $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtub VRRC:$vA, VRRC:$vB))]>;
+def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtub. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+
+// i16 element comparisons.
+def VCMPEQUH : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequh $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpequh VRRC:$vA, VRRC:$vB))]>;
+def VCMPEQUHo : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequh. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTSH : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsh $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtsh VRRC:$vA, VRRC:$vB))]>;
+def VCMPGTSHo : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsh. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTUH : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtuh $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtuh VRRC:$vA, VRRC:$vB))]>;
+def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtuh. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+
+// i32 element comparisons.
+def VCMPEQUW : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequw $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpequw VRRC:$vA, VRRC:$vB))]>;
+def VCMPEQUWo : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpequw. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTSW : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsw $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtsw VRRC:$vA, VRRC:$vB))]>;
+def VCMPGTSWo : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtsw. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+def VCMPGTUW : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtuw $vD, $vA, $vB", VecFPCompare,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcmpgtuw VRRC:$vA, VRRC:$vB))]>;
+def VCMPGTUWo : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vcmpgtuw. $vD, $vA, $vB", VecFPCompare,
+ []>, isVDOT;
+
def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
"vxor $vD, $vD, $vD", VecFP,
[(set VRRC:$vD, (v4f32 vecimm0))]>;
Index: llvm/lib/Target/PowerPC/PPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.68 llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.69
--- llvm/lib/Target/PowerPC/PPCInstrFormats.td:1.68 Sat Mar 25 18:41:48 2006
+++ llvm/lib/Target/PowerPC/PPCInstrFormats.td Sat Mar 25 22:57:17 2006
@@ -664,19 +664,20 @@
}
// E-4 VXR-Form
-class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
+class VXRForm_1<bits<10> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<4, OL, asmstr, itin> {
bits<5> VD;
bits<5> VA;
bits<5> VB;
+ bit RC = 0;
let Pattern = pattern;
let Inst{6-10} = VD;
let Inst{11-15} = VA;
let Inst{16-20} = VB;
- let Inst{21} = rc;
+ let Inst{21} = RC;
let Inst{22-31} = xo;
}
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