[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.175 -> 1.176
---
Log message:

Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll


---
Diffs of the changes:  (+14 -4)

 PPCISelDAGToDAG.cpp |   18 ++++++++++++++----
 1 files changed, 14 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.175 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.176
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.175	Tue Mar 21 23:26:03 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Fri Mar 24 11:58:06 2006
@@ -616,11 +616,21 @@
   // Check to see if we can easily represent this as an [r+r] address.  This
   // will fail if it thinks that the address is more profitably represented as
   // reg+imm, e.g. where imm = 0.
-  if (!SelectAddrIdx(N, Base, Index)) {
-    // Nope, do it the hard way.
-    Base = CurDAG->getRegister(PPC::R0, MVT::i32);
-    Index = N;
+  if (SelectAddrIdx(N, Base, Index))
+    return true;
+  
+  // If the operand is an addition, always emit this as [r+r], since this is
+  // better (for code size, and execution, as the memop does the add for free)
+  // than emitting an explicit add.
+  if (N.getOpcode() == ISD::ADD) {
+    Base = N.getOperand(0);
+    Index = N.getOperand(1);
+    return true;
   }
+  
+  // Otherwise, do it the hard way, using R0 as the base register.
+  Base = CurDAG->getRegister(PPC::R0, MVT::i32);
+  Index = N;
   return true;
 }